Differential stage voltage offset trim circuitry

A differential stage, comprising:

• a main differential pair comprising first and second transistors, each of which has a control input and first and second current terminals, said second current terminals connected together at a first node;
• a first bias current source connected to said first node which provides a first bias current to said main differential pair such that said first and second transistors conduct respective output currents at their first current terminals in response to a differential input voltage applied across their control inputs, said first differential pair having an associated common-mode input voltage;
• a second differential pair comprising third and fourth transistors, each of which has a control input and first and second current terminals, said second current terminals connected together at a second node;
• a second bias current source connected to provide a second bias current to said second differential pair;
• circuitry connected to said second differential pair and arranged to make said second differential pair's common-mode input voltage approximately equal to said main pair's common-mode input voltage;
• and
• first and second trim current sources arranged to provide respective currents I1 and I2 to the control inputs of said third and fourth transistors, respectively, to create a desired differential voltage across said second differential pair such that said third and fourth transistors conduct respective trim currents Itrim1 and Itrim2, said trim currents coupled to respective ones of said output currents.

A differential input stage, comprising:

• a main differential pair comprising first and second transistors and biased with a first bias current such that said main pair conducts respective output currents in response to a differential input voltage;
• at least one voltage offset trim circuit, said at least one voltage offset trim circuit comprising:
• a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to mismatch between the threshold voltages of said first and second transistors, comprising in addition to said main differential pair:
• a second differential transistor pair;
• circuitry connected to said second differential transistor pair and arranged to make said second pair's common-mode input voltage approximately equal to said main pair's common-mode input voltage;
• and
• first and second programmable current sources connected to create a desired differential voltage across said second differential transistor pair such that the transistors of said second pair conduct respective trim currents, said trim currents coupled to respective ones of said output currents, said first and second programmable current sources programmed such that said trim currents substantially reduce voltage offset error in said main differential pair which arises due to the transistors of said main pair having mismatched threshold voltages;
• and/or
• a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to beta mismatch between said first and second transistors, comprising in addition to said main differential pair:
• a second differential transistor pair biased with a second bias current such that said second pair conducts respective output currents in response to said differential input voltage, wherein the ratio between said second and first bias currents is approximately 1:N and the ratio between the sizes of said main pair transistors with respect to the sizes of said second pair transistors, respectively, is approximately 1:N, such that said second pairs' output currents are proportional to said main pairs' average drain current;
• and
• a digital-to-analog converter (DAC) connected to receive said second pairs' output currents at a reference current input and arranged to produce trim currents at respective current outputs, said trim currents varying with said second pairs' output currents and thus said main pairs' average drain current and scaled by a digital value applied to said DAC's digital input, said trim currents coupled to respective ones of said main pair's output currents, said DAC programmed to reduce voltage offset error in said main differential pair that arises due to beta mismatch between the transistors of said main pair;
• and/or
• a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to gamma mismatch between said first and second transistors, comprising in addition to said main differential pair:
• circuitry which receives said differential input voltage and is arranged to produce a reference current which varies linearly or linearly with an additive constant with the stage's source voltage relative to ground;
• a digital-to-analog converter (DAC) connected to receive said reference current at a reference current input and arranged to produce currents I1 and I2 at respective current outputs, said currents varying with said reference current and scaled by a digital value applied to said DAC's digital input;
• and
• a second differential transistor pair which receives currents I1 and I2 and is biased to conduct respective trim currents in response, said trim currents coupled to respective ones of said main pair's output currents, said DAC programmed to reduce voltage offset error in said main pair that arises due to gamma mismatch between the transistors of said main pair;
• and/or
• a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to threshold mismatch between the transistors of an active load driven by said main differential pair, comprising in addition to said main differential pair:
• an active load comprising third and fourth transistors connected in series between a supply voltage and said first and second transistors, respectively, said active load transistors biased with a bias voltage such that they conduct said output currents;
• a second differential pair comprising fifth and sixth transistors and biased with said bias voltage;
• and
• first and second programmable current sources arranged to provide respective currents I1 and I2 to said fifth and sixth transistors, respectively, to create a desired differential voltage across said second differential pair such that said fifth and sixth transistors conduct respective trim currents, said trim currents coupled to respective ones of said output currents, said first and second trim current sources programmed to produce trim currents I1 and I2 to match the currents conducted by said third and fourth transistors and to thereby reduce voltage offset error in said main differential pair which arises due to said active load transistors having mismatched threshold voltages;
• and/or
• a trim circuit adjusted to reduce voltage offset error in said main differential pair that arises due to beta mismatch between the transistors of an active load driven by said main differential pair, comprising in addition to said main differential pair:
• an active load comprising third and fourth transistors connected in series between a supply voltage and said first and second transistors, respectively, said active load transistors biased with a bias voltage such that they conduct said output currents;
• a fifth transistor connected to said supply voltage and said bias voltage such that said fifth transistor is biased like said active load transistors and conducts a reference current which varies with said bias voltage;
• and
• a digital-to-analog converter (DAC) connected to receive said reference current at a reference current input and arranged to produce first and second trim currents at respective current outputs, said currents varying with said reference current and scaled by a digital value applied to said DAC's digital input;
• said trim currents coupled to respective ones of said main pair's output currents, said DAC programmed to match the currents conducted by said third and fourth transistors and to thereby reduce voltage offset error in said main differential pair that arises due to beta mismatch between said third and fourth transistors.

A method of reducing voltage offset error that arises due to a mismatch between the threshold voltages of a main FET differential pair biased to conduct respective output currents in response to a differential input voltage, comprising:

• providing a second FET differential pair;
• making said second pair's common-mode input voltage approximately equal to said main pair's common-mode input voltage;
• providing first and second programmable currents to said second pair to create a desired differential voltage across said second pair such that the FETs of said second pair conduct respective trim currents;
• coupling said trim currents to respective ones of said output currents;
• and
• adjusting said first and second programmable currents such that said trim currents reduce voltage offset error in said main differential pair which arises due to the transistors of said main pair having mismatched threshold voltages.