Semiconductor heterostructures and related methods
AssigneeAmberWave Systems Corporation
InventorsChristopher Vineis, Vicky Yang, Matthew Currie, Richard Westhoff, Christopher Leitz
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Abstract
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
Claims21
A method of forming a relaxed graded semiconductor layer on a substrate, the method comprising the steps of:
- providing a first semiconductor layer;
- and
- epitaxially growing over the first semiconductor layer a relaxed graded layer comprising at least one of silicon and germanium, with increasing germanium content at a grading rate exceeding about 25% Ge/μm to a final composition having a germanium content ranging from greater than 0% to 100% and a threading dislocation density not exceeding about 107/cm2.
A semiconductor structure comprising a first semiconductor layer and, thereover, a relaxed graded epitaxial layer comprising silicon and germanium and graded with increasing germanium content at a grading rate exceeding 25% Ge/μm to a final composition having a germanium content ranging from greater than 0% to 100%, wherein the structure has a threading dislocation density not exceeding 107/cm2.
A semiconductor structure comprising:
- a first semiconductor layer and, thereover, a relaxed graded epitaxial layer comprising silicon and germanium and graded with increasing germanium content at a grading rate exceeding 25% Ge/μm to a final composition having a germanium content ranging from greater than 0% to 100%, wherein the structure has a threading dislocation density not exceeding 107/cm2;
- a relaxed compositionally uniform cap layer disposed over the relaxed graded epitaxial layer;
- and
- a p-type metal-oxide-semiconductor (PMOS) transistor disposed over the relaxed compositionally uniform cap layer, the PMOS transistor including:
- a gate dielectric portion disposed over a portion of the relaxed cap layer,
- a gate disposed over the gate dielectric portion, the gate comprising a conducting layer, and
- a source and a drain disposed proximate the gate dielectric portion, the source and first drain including p-type dopants.
A semiconductor structure comprising:
- a first semiconductor layer and, thereover, a relaxed graded epitaxial layer comprising silicon and germanium and graded with increasing germanium content at a grading rate exceeding 25% Ge/μm to a final composition having a germanium content ranging from greater than 0% to 100%, wherein the structure has a threading dislocation density not exceeding 107/cm2;
- a relaxed compositionally uniform cap layer disposed over the relaxed graded epitaxial layer;
- and
- an n-type metal-oxide-semiconductor (NMOS) transistor disposed over the relaxed compositionally uniform cap layer, the NMOS transistor including:
- a gate dielectric portion disposed over a portion of the relaxed compositionally uniform cap layer,
- a gate disposed over the gate dielectric portion, the gate comprising a conducting layer,
- a source and a drain disposed proximate the gate dielectric portion, the source and drain including n-type dopants.
A semiconductor structure comprising:
- a first semiconductor layer and, thereover, a relaxed graded epitaxial layer comprising silicon and germanium and graded with increasing germanium content at a grading rate exceeding 25% Ge/μm to a final composition having a germanium content ranging from greater than 0% to 100%, wherein the structure has a threading dislocation density not exceeding 107/cm2;
- a relaxed compositionally uniform cap layer disposed over the relaxed graded epitaxial layer;
- a p-type metal-oxide-semiconductor (PMOS) transistor disposed over the relaxed compositionally uniform cap layer, the PMOS transistor including:
- a first gate dielectric portion disposed over a first portion of the relaxed compositionally uniform cap layer,
- a first gate disposed over the first gate dielectric portion, the first gate comprising a first conducting layer,
- a first source and a first drain disposed proximate the first gate dielectric portion, the first source and first drain including p-type dopants;
- and
- an n-type metal-oxide-semiconductor (NMOS) transistor disposed over the relaxed compositionally uniform cap layer, the NMOS transistor including:
- a second gate dielectric portion disposed over a second portion of the relaxed compositionally uniform cap layer,
- a second gate disposed over the second gate dielectric portion, the second gate comprising a second conducting layer,
- a second source and a second drain disposed proximate the second gate dielectric portion, the second source and second drain including n-type dopants.
Dependencies are inferred from the claim text.