Cross-point memory architecture with improved selectivity

A cross-point memory array, comprising:

• a plurality of memory cells;
• a plurality of global word lines, at least a given one of the global word lines being configurable for conveying a write current for selectively writing a logical state of one or more of the plurality of memory cells;
• a plurality of local word lines, each of the local word lines being connected to at least one of the plurality of memory cells for assisting in writing a logical state of the at least one memory cell corresponding thereto;
• a plurality of selection circuits, each of the selection circuits being operative to electrically connect a given one of the local word lines to a given one of the global word lines in response to a control signal applied thereto;
• a plurality of global bit lines, each of the global bit lines being connected to at least one of the plurality of memory cells for writing a logical state of the at least one memory cell corresponding thereto;
• wherein the memory array is configured such that, during a write operation for writing at least a given one of the memory cells, global bit lines corresponding to unselected memory cells charge local word lines corresponding to the unselected memory cells to a standby voltage, whereby each of the unselected memory cells has substantially zero volts across it.

An integrated circuit device including at least one memory array, the at least one memory array comprising:

• a plurality of memory cells;
• a plurality of global word lines, at least a given one of the global word lines being configurable for conveying a write current for selectively writing a logical state of one or more of the plurality of memory cells;
• a plurality of local word lines, each of the local word lines being connected to at least one of the plurality of memory cells for assisting in writing a logical state of the at least one memory cell corresponding thereto;
• a plurality of selection circuits, each of the selection circuits being operative to electrically connect a given one of the local word lines to a given one of the global word lines in response to a control signal applied thereto;
• a plurality of global bit lines, each of the global bit lines being connected to at least one of the plurality of memory cells for writing a logical state of the at least one memory cell corresponding thereto;
• wherein the memory array is configured such that during a write operation directed to at least one selected memory cell, the write current passes through the selected memory cell for writing the logical state of the selected memory cell.