Back to results
US 7,045,851 B2Granted
Nonvolatile memory device using semiconductor nanocrystals and method of forming same
AssigneeInternational Business Machines Corporation
InventorsCharles T. Black, Kathryn Wilder Guarini
Life of this patent
Estimating the term…
Abstract
A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.
Claims27
A floating gate for a field effect transistor, comprising:
- a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is at least one of templated and defined by a self-assembled material,
- wherein said nanoparticles comprise a substantially uniform diameter, said nanoparticles comprising diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of a mean diameter of the nanoparticles,
- wherein said nanoparticles comprise a substantially uniform center-to-center spacing between said nanoparticles, and
- wherein said nanoparticles are arranged in a two-dimensional array.
1 more element
A field effect transistor, comprising:
- a source region and a drain region formed in a semiconductor material;
- a channel region disposed between said source region and said drain region;
- an insulating layer of electrically insulating material disposed over said channel region;
- a floating gate layer of electrically conducting material disposed over said insulating layer;
- a layer of electrically insulating material disposed over said floating gate layer;
- and
- a gate electrode overlying said layer of insulating material,
- wherein said floating gate layer comprises a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is one of templated and defined by a self-assembled material,
- wherein said nanoparticles comprise a substantially uniform diameter, said nanoparticles comprising diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of a mean diameter of the nanoparticles,
- wherein said nanoparticles comprise a substantially uniform center-to-center spacing between said nanoparticles, and
- wherein said nanoparticle density is greater than 1010/cm2.
8 more elements
A floating gate for a field effect transistor, comprising:
- a plurality of discrete nanoparticles in which at least one of a size, spacing and density of said nanoparticles is at least one of templated and defined by a self-assembled material,
- wherein said nanoparticles comprise diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of a mean diameter of the nanoparticles, and
- wherein a center-to-center spacing between adjacent nanoparticles is controlled to comprise a variance within a range of about 10% to about 20%.
A field effect transistor, comprising:
- a source region and a drain region formed in a semiconductor material;
- a channel region disposed between said source region and said drain region;
- an insulating layer of electrically insulating material disposed over said channel region;
- a floating gate layer of electrically conducting material disposed over said insulating layer;
- a layer of electrically insulating material disposed over said floating gate layer;
- and
- a gate electrode overlying said layer of insulating material,
- wherein said floating gate layer comprises a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is at least one of templated and defined by a self-assembled material, and
- wherein said nanoparticles are arranged in a close-packed, two-dimensional hexagonal lattice.
6 more elements
A field effect transistor, comprising:
- a source region and a drain region formed in a semiconductor material;
- a channel region disposed between said source region and said drain region;
- an insulating layer of electrically insulating material disposed over said channel region;
- a floating gate layer of electrically conducting material disposed over said insulating layer;
- a layer of electrically insulating material disposed over said floating gate layer;
- and
- a gate electrode overlying said layer of insulating material,
- wherein said floating gate layer comprises a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is at least one of templated and defined by a self-assembled material,
- wherein said nanoparticles are arranged in a close-packed, two-dimensional hexagonal lattice, and
- wherein said hexagonal lattice comprises an average inter-nanoparticle distance between about 1 times and about 2 times an average nanoparticle diameter, and a standard deviation of inter-nanoparticle distance no greater than substantially 20% of the mean distance.
7 more elements
A field effect transistor, comprising:
- a source region and a drain region formed in a semiconductor material;
- a channel region disposed between said source region and said drain region;
- an insulating layer of electrically insulating material disposed over said channel region;
- a floating gate layer of electrically conducting material disposed over said insulating layer;
- a layer of electrically insulating material disposed over said floating gate layer;
- and
- a gate electrode overlying said layer of insulating material,
- wherein said floating gate layer comprises a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of said nanoparticles is at least one of templated and defined by a self-assembled material, and
- wherein said nanoparticles in said floating gate comprise a first distinct size and a second distinct size, each with diameter standard deviations being less than approximately 15% of a mean diameter of said nanoparticles.
6 more elements
A floating gate for a field effect transistor, comprising:
- a plurality of discrete nanoparticles, wherein said nanoparticles have diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of mean diameter of the nanoparticles,
- wherein a center-to-center spacing between adjacent nanoparticles is controlled to comprise a variance within a range of no greater than about 20%, and
- wherein said nanoparticles are arranged in a two-dimensional array.
A field effect transistor, comprising:
- a floating gate, comprising:
- a plurality of discrete nanoparticles, wherein said nanoparticles have diameters between about 2 nanometers and about 30 nanometers, with size distributions no greater than about 15% of mean diameter of the nanoparticles,
- wherein a center-to-center spacing between adjacent nanoparticles is controlled to comprise a variance within a range of no greater than about 20%, and
- wherein said nanoparticles are arranged in a two-dimensional array.
1 more element
A floating gate for a field effect transistor, comprising:
- a plurality of discrete nanoparticles,
- wherein said nanoparticles are arranged in a close-packed, two-dimensional hexagonal lattice.
A field effect transistor, comprising:
- a floating gate, comprising:
- a plurality of discrete nanoparticles,
- wherein said nanoparticles are arranged in a close-packed, two-dimensional hexagonal lattice.
Dependencies are inferred from the claim text.