Stackable semiconductor package and method for manufacturing same

A method of fabricating a semiconductor package, comprising the steps of:

• a) providing a leadframe comprising:
• a die paddle defining opposed, generally planar top and bottom surfaces;
• a first set of leads extending at least partially about the die paddle in spaced relation thereto;
• and
• a second set of leads extending at least partially about the leads of the first set in spaced relation thereto, each of the leads of the first and second sets having an upper portion defining a generally planar top side and a first end, a lower portion defining a generally planar bottom side and a second end, and a middle portion extending between the upper and lower portions, the transition from the first end to the second end in each of the leads of the first and second sets occuring without the lower portion reversing direction to extend along the upper portion;
• b) attaching a semiconductor chip to the top surface of the die paddle;
• c) electrically connecting the semiconductor chip to at least one of the leads of each of the first and second sets;
• and
• d) partially encapsulating the leadframe and the semiconductor chip with a sealing material such that the bottom sides of the lower portions of the leads of the first and second sets and the top sides of the upper portions of the leads of the first and second sets are exposed in the sealing material.

A method of fabricating a chip stack, comprising the steps of:

• a) providing first and second semiconductor packages, each of which comprises:
• a die paddle defining opposed, generally planar top and bottom surfaces;
• a plurality of leads extending at least partially about the die paddle in spaced relation thereto, each of the leads having an upper portion defining a generally planar top side and first end, a lower portion defining a generally planar bottom side, and a middle portion extending between the upper and lower portions, the transition from the first end to the second end in each of the leads occurring without the lower portion reversing direction to extend along the upper portion;
• a semiconductor chip attached to the top surface of the die paddle and electrically connected to at least one of the leads;
• and
• a sealing material at least partially encapsulating the leadframe and the semiconductor chip such that the bottom sides of the lower portions of the leads and the top sides of the upper portions of the leads are exposed in the sealing material;
• and
• b) electrically connecting the top sides of the upper portions of the leads of the first semiconductor package to respective ones of the top sides of the upper portions of the leads of the second semiconductor package.

A method of fabricating a chip stack, comprising the steps of:

• a) providing first and second semiconductor packages, each of which comprises:
• a die paddle defining opposed, generally planar top and bottom surfaces;
• a first set of leads extending at least partially about the die paddle in spaced relation thereto;
• a second set of leads extending at least partially about the leads of the first set in spaced relation thereto, each of the leads of the first and second sets having an upper portion defining a generally planar top side and a first end, a lower portion defining a generally planar bottom side and a second end, and a middle portion extending between the upper and lower portions the transition from the first end to the second end in each of the leads of the first and second sets occurring without the lower portion reversing direction to extend along the upper portion;
• a semiconductor chip attached to the top surface of the die paddle and electrically connected to at least one of the leads of each of the first and second sets;
• and
• a sealing material at least partially encapsulating the leadframe and the semiconductor chip such that the bottom sides of the lower portions of the leads of the first and second sets and the top sides of the upper portions of the leads of the first and second sets are exposed in the sealing material;
• b) electrically connecting the bottom sides of the lower portions of the leads of the first set of the first semiconductor package to respective ones of the bottom sides of the lower portions of the leads of the first set of the second semiconductor package;
• and
• c) electrically connecting the bottom sides of the lower portions of the leads of the second set of the first semiconductor package to respective ones of the bottom sides of the lower portions of the leads of the second set of the second semiconductor package.