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US 7,042,789 B2Granted
Energy storing memory circuit
AssigneeInfineon Technologies AG
InventorJoachim Bangert
Life of this patent
Estimating the term…
Abstract
The invention relates to a memory arrangement having an energy storage device (store) which collects the energy transported during the flowing of a write or read current and makes it available for a new write or read operation.
Claims20
A memory circuit for reduced energy loss comprising:
- a memory cell array containing a plurality of memory cells, each memory cell connected to a word line and bit line;
- and
- at least one generator device configured to feed a current into a bit line and/or wordline assigned to a memory cell during reading or writing the memory cell, wherein the generator device comprises an energy storage system that collects the energy transported by the current flowing during an addressing process, so that the energy is available for subsequent addressing of memory cells, and wherein the energy storage system is configured to change over between an energy take-up state and an energy release state in a clock-controlled manner.
A memory circuit for reduced energy loss comprising:
- a memory cell array containing a plurality of memory cells, each memory cell connected to a word line and bit line;
- and
- at least one generator device configured to feed a current into a bit line and/or wordline assigned to a memory cell during reading or writing the memory cell, wherein the generator device comprises an energy storage system that collects the energy transported by the current flowing during an addressing process, so that the energy is available for subsequent addressing of memory cells, wherein the energy storage system comprises energy storage units arranged on opposite sides of the memory cell array.
A memory architecture for reducing energy consumption in memory operation comprising:
- a memory array containing memory cells addressable by bit lines and wordlines;
- at least one pair of energy storage units for storing and delivering energy to the memory array that is used in addressing operations, wherein each energy storage unit of the pair lies on an opposite side of the memory array from the other storage unit;
- and
- a mutliplexer coupled to the energy units such that energy can be delivered to and from individual wordlines or bitlines used to address a memory cell, wherein each energy storage unit comprises at least two capacitors that be alternately arranged as a series capacitor circuit or as a parallel capacitor circuit by means of a switch.
1 more element
Dependencies are inferred from the claim text.