Memory bit line segment isolation
AssigneeFreescale Semiconductor, Inc.
InventorsJames M. Sibigtroth, George L. Espinor, Bruce L. Morton
Life of this patent
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Abstract
A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being erased. In one example, the isolation circuit (16) electrically couples the segments during a read or program of memory cells located on the second segment (Seg2 BL0). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.
Claims24
A memory comprising:
- a bit line including a first segment and a second segment;
- a first memory cell located on the first segment;
- a second memory cell located on the second segment;
- and
- an isolation circuit, the first segment selectively coupled to the second segment via the isolation circuit, the isolation circuit decoupling the first segment and the second segment when the second memory cell is being erased and the first memory cell is being read, and coupling the first segment and the second segment when the second memory cell is being read.
A method of operating a memory, the memory including a bit line, the bit line including a first segment and a second segment, the memory including a first memory cell located on the first segment and a second memory cell located on the second segment, the method comprising:
- electrically isolating the first segment from the second segment;
- erasing the second memory cell with the first segment being isolated from the second segment;
- reading the first memory cell during the erasing;
- and
- electrically coupling the first segment to the second segment for reading the second memory cell.
A memory comprising:
- a bit line comprising a first segment and a second segment;
- a first plurality of memory cells located on the first segment;
- a second plurality of memory cells located on the second segment;
- and
- means for isolating the first segment from the second segment when any memory cell of the second plurality of memory cells is being erased and a memory cell of the first plurality of memory cells is being read, and for electrically coupling the first segment to the second segment when any memory cell of the second plurality of memory cells is being read.
A memory comprising:
- a bit line comprising a first segment and a second segment;
- a first plurality of memory cells located on the first segment;
- a second plurality of memory cells located on the second segment;
- a sense amplifier coupled to the bit line, the sense amplifier functioning for both the first segment and the second segment of the bit line;
- and
- an isolation circuit, the first segment being selectively coupled to the second segment via the isolation circuit, wherein the isolation circuit isolates the first segment from the second segment when any memory cell of the second plurality is being erased and a memory cell of the first plurality is being read, wherein the first segment is electrically coupled to the second segment via the isolation circuit when any memory cell of the second plurality is being read.
Dependencies are inferred from the claim text.