Return-to-zero current switching digital-to-analog converter

A current switching digital-to-analog converter (DAC), comprising:

• a differential analog output comprising first and second output lines for which a “zero” potential has been defined, said differential analog output providing said DAC's analog output voltage;
• a first clock signal CK;
• a second clock signal {overscore (CK)} which is the inverse of said first clock signal;
• clocked circuitry which receives said first clock signal CK and a digital input comprising a plurality of digital bits representative of a desired analog output voltage, and provides as outputs a plurality of control signals the states of which vary with said digital bits, said control signals changing state in synchronization with said first clock signal CK;
• a plurality of current sources having respective outputs;
• a plurality of pairs of intermediate nodes, each comprising first and second intermediate nodes;
• a plurality of data current switches arranged to direct respective current source outputs to the first or second intermediate node of a respective one of said pairs of intermediate nodes, each of said pairs of data current switches comprising:
• a first transistor arranged to direct said current source output to the first intermediate node of said pair of intermediate nodes in response to a respective one of said control signals, and
• a second transistor arranged to direct said current source output to the second intermediate node of said pair of intermediate nodes in response to a respective one of said control signals;
• a control signal;
• a plurality of pairs of return-to-zero (RZ) circuits connected between respective pairs of said intermediate nodes and said first and second output lines,
• each of said pairs of RZ circuits comprising:
• a first RZ circuit comprising:
• a first transistor connected between the first intermediate node of said pair of intermediate nodes and one of said first and second analog output lines and driven with a fixed bias voltage Vbias, and
• a second transistor connected between said first intermediate node and circuit ground and driven with said control signal;
• and
• a second RZ circuit comprising:
• a first transistor connected between the second intermediate node of said pair of intermediate nodes and the other of said first and second analog output lines and driven with said fixed bias voltage Vbias, and
• a second transistor connected between said second intermediate node and circuit ground and driven with said control signal;
• and
• first and second output networks connected to said first and second analog output lines, respectively, and arranged such that said analog output lines are pulled to said “zero” potential when said intermediate nodes are directed to circuit ground via said RZ circuits;
• said DAC arranged such that said control signal toggles above and below Vbias in synchronization with said CK signal, such that, when said control signal toggles below Vbias, said second transistors turn off and said first transistors turn on and direct current to said analog output nodes, and when said control signal toggles above Vbias, said first transistors turn off and said second transistors turn on and direct current to said circuit ground when said control signal toggles above Vbias, such that switching noise that arises when said clock signal CK is asserted is prevented from appearing on said analog output nodes.

A current switching digital-to-analog converter (DAC), comprising:

• an analog output line for which a “zero” potential has been defined which provides said DAC's analog output voltage;
• a first clock signal CK;
• clocked circuitry which receives said first clock signal CK and a digital input comprising a plurality of digital bits representative of a desired analog output voltage, and provides as outputs a plurality of control signals the states of which vary with said digital bits, said control signals changing state in synchronization with said first clock signal CK;
• a plurality of current sources having respective outputs;
• a plurality of pairs of intermediate nodes, each comprising first and second intermediate nodes, each of said second intermediate nodes connected to circuit ground;
• a plurality of data current switches arranged to direct respective current source outputs to the first or second intermediate node of a respective one of said pairs of intermediate nodes, each of said pairs of data current switches comprising:
• a first transistor arranged to direct said current source output to the first intermediate node of said pair of intermediate nodes in response to a respective one of said control signals, and
• a second transistor arranged to direct said current source output to the second intermediate node of said pair of intermediate nodes in response to a respective one of said control signals;
• a control signal;
• a plurality of return-to-zero (RZ) circuits connected between respective ones of said first intermediate nodes and said analog output line, each of said RZ circuits comprising:
• a first transistor connected between said first intermediate node and said analog output line and driven with a fixed bias voltage Vbias, and
• a second transistor connected between said first intermediate node and circuit ground and driven with said control signal;
• said DAC arranged such that said control signal toggles above and below Vbias, when said control signal toggles below Vbias, said second transistor turns off and said first transistor turns on and directs current to said analog output node, and when said control signal toggles above Vbias, said first transistor turns off and said second transistor turns on and directs current to said fixed voltage;
• and
• an output network connected to said analog output line and arranged such that said analog output line is pulled to said “zero” potential when said first intermediate nodes are directed to circuit ground via said RZ circuits, such that said RZ circuits prevent switching noise that arises when said clock signal CK is asserted from appearing on said analog output line.