Gated lateral thyristor-based random access memory cell (GLTRAM)

A memory cell, comprising:

• an access transistor having a drain region, a raised source region, and a gate;
• and
• a gated, lateral thyristor integrally formed above the access transistor such that a first end of the thyristor is formed with the raised source region of the access transistor,
• wherein a portion of the thyristor is formed by depositing a thin layer of amorphous silicon and re-crystallizing the silicon using a metal-induced lateral crystallization technique (MILC).

A memory cell, comprising:

• an access transistor, including a drain region to electrically connect with a bit line, a raised source region, and a gate to electrically connect with a first word line;
• and
• a lateral thyristor integrated with and formed over the access transistor, the lateral thyristor having a first end formed with the raised source region of the access transistor, a second end to electrically connect with a reference voltage, and a thyristor gate to electrically connect with a second word line to assist with switching of the thyristor,
• wherein a portion of the thyristor is formed by depositing a thin layer of amorphous silicon and re-crystallizing the silicon using a metal-induced lateral crystallization technique (MILC).

A memory cell, comprising:

• an n-channel access field effect transistor having an n+ drain region, a raised n+ source region, and a gate;
• and
• a gated, lateral p+/n/p/n+ thyristor integrally formed above the n-channel access field effect transistor such that a cathode of the thyristor is formed with the raised n+ source region of the n-channel access field effect transistor,
• wherein a portion of the thyristor is formed by depositing a thin layer of amorphous silicon and re-crystallizing the silicon using a metal-induced lateral crystallization technique (MILC).

A memory cell array, including a number of memory cells arranged in a number of rows and a number of columns,

• each of the number of memory cells, including:
• an access transistor having a drain region, a raised source region, and a gate;
• and
• a gated, lateral thyristor integrally formed above the access transistor such that a first end of the thyristor is formed with the raised source region of the access transistor;
• and
• each row including a first memory cell, a second memory cell and a third memory cell,
• wherein a bit line contact is in electrical contact with the drain region of the first memory cell and in electrical contact with the drain region of the second memory cell, and a thyristor gate is positioned to assist in the switching of the thyristor of the third memory cell and the thyristor of the second memory cell,
• wherein a portion of the thyristor for each of the memory cells is formed by depositing a thin layer of amorphous silicon and re-crystallizing the silicon using a metal-induced lateral crystallization technique (MILC).

A memory cell array, including a number of memory cells arranged in a number of rows and a number of columns,

• each of the number of memory cells, including:
• an access transistor having a drain region, a raised source region, and a gate;
• and
• a gated, lateral thyristor integrally formed above the access transistor such that a first end of the thyristor is formed with the raised source region of the access transistor, the lateral thyristor including a cathode region and an anode region with a number of dopant regions therebetween, the thyristor having a geometry such that every dopant region between the cathode region and the anode region is in contact with and laterally adjacent to at least one other dopant region between the cathode region and the anode region, the lateral thyristor including one of the dopant regions in electrical contact with and laterally adjacent to a portion of the raised source region;
• and
• each row including a first memory cell, a second memory cell and a third memory cell, wherein a bit line contact is in electrical contact with the drain region of the first memory cell and in electrical contact with the drain region of the second memory cell, and a thyristor gate is positioned to assist in the switching of the thyristor of the third memory cell and the thyristor of the second memory cell.

A memory cell array, including a number of memory cells arranged in a number of rows and a number of columns,

• each of the number of memory cells, including:
• an access transistor, including a drain region to electrically connect with a bit line, a raised source region, and a gate to electrically connect with a first word line;
• and
• a lateral thyristor integrated with and formed over the access transistor, the lateral thyristor having a first end formed with the raised source region of the access transistor and a second end to electrically connect with a reference voltage, the lateral thyristor including a cathode region and an anode region with a number of dopant regions therebetween, the thyristor having a geometry such that every dopant region between the cathode region and the anode region is in contact with and laterally adjacent to at least one other dopant region between the cathode region and the anode region, the lateral thyristor including one of the dopant regions in electrical contact with and laterally adjacent to a portion of the raised source region;
• each row including a first memory cell, a second memory cell and a third memory cell, wherein a bit line contact is in electrical contact with the drain region of the first memory cell and in electrical contact with the drain region of the second memory cell, and a thyristor gate is positioned to assist in the switching of the thyristor of the third memory cell and the thyristor of the second memory cell.

A memory cell array, including a number of memory cells arranged in a number of rows and a number of columns,

• each of the number of memory cells, including:
• an access transistor, including a drain region to electrically connect with a bit line, a raised source region, and a gate to electrically connect with a first word line;
• and
• a lateral thyristor integrated with and formed over the access transistor, the lateral thyristor having a first end formed with the raised source region of the access transistor and a second end to electrically connect with a reference voltage;
• each row including a first memory cell, a second memory cell and a third memory cell, wherein a bit line contact is in electrical contact with the drain region of the first memory cell and in electrical contact with the drain region of the second memory cell, and a thyristor gate is positioned to assist in the switching of the thyristor of the third memory cell and the thyristor of the second memory cell,
• wherein a portion of the thyristor for each of the memory cells is formed by depositing a thin layer of amorphous silicon and re-crystallizing the silicon using a metal-induced lateral crystallization technique (MILC).

A memory cell array, formed by a process comprising:

• forming an access transistor with a raised source region using a selective epitaxy process for each of a first memory cell, a second memory cell, and a third memory cell;
• forming a portion of a lateral thyristor integrally formed above the access transistor for each of the first memory cell, the second memory cell, and the third memory cell by depositing a thin layer of amorphous silicon and re-crystallizing the silicon using a metal-induced-lateral-crystallization (MILC) technique, wherein a first end of the thyristor is formed with the raised source region of the access transistor;
• forming a single bit line contact in contact with a drain region of the access transistor for the first memory cell and in contact with a drain region of the access transistor for the second memory cell;
• and
• forming a single thyristor gate to assist with switching the lateral thyristor of the second memory cell and with switching the lateral thyristor of the third memory cell.

An electronic system, comprising:

• a processor;
• and
• a memory device to communicate with the processor, wherein the memory device includes an array of memory cells, wherein each memory cell comprises:
• an access transistor having a drain region, a raised source region, and a gate;
• and
• a gated, lateral thyristor integrally formed above the access transistor such that a first end of the thyristor is formed with the raised source region of the access transistor, the lateral thyristor including a cathode region and an anode region with a number of dopant regions therebetween, the thyristor having a geometry such that every dopant region between the cathode region and the anode region is in contact with and laterally adjacent to at least one other dopant region between the cathode region and the anode region, the lateral thyristor including one of the in electrical contact with and laterally adjacent to a portion of the raised source region.

An electronic system, comprising:

• a processor;
• and
• a memory device to communicate with the processor, wherein the memory device includes an array of memory cells, wherein each memory cell comprises:
• an access transistor having a drain region, a raised source region, and a gate;
• and
• a gated, lateral thyristor integrally formed above the access transistor such that a first end of the thyristor is formed with the raised source region of the access transistor,
• wherein a portion of the thyristor is formed by depositing a thin layer of amorphous silicon and re-crystallizing the silicon using a metal-induced lateral crystallization technique (MILC).