Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration
AssigneeIntel Corporation
InventorsScot A. Kellar, Sarah E. Kim, R. Scott List
Life of this patent
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AssigneeIntel Corporation
InventorsScot A. Kellar, Sarah E. Kim, R. Scott List
Estimating the term…
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.
A wafer bonding method, comprising:
Dependencies are inferred from the claim text.