Algorithm to increase logic input width by cascading product terms
AssigneeLattice Semiconductor Corporation
InventorsGilles Bosco, Hua Xue
Life of this patent
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Abstract
An algorithm is disclosed to partition input variables between a feeder logic block and a receiver logic block. For a given input variable partition, the algorithm assigns both a cost to the number of product terms cascaded from the feeder logic block to the receiver logic block as well as a cost that increases as the number of input variables assigned to the receiver logic block approaches its maximum input width. The costs for a variety of input variable partitions are tested to determine an optimal input variable partition.
Claims14
A method for assigning input variables between a feeder logic block and a receiver logic block to implement a logic function, wherein the input width of the logic function exceeds a maximum input width for both the feeder logic block and the receiver logic block, the method comprising:
- providing a cost function that assigns a first cost to a number of product terms cascaded from the feeder logic block to the receiver logic block and also assigns a second cost that increases as a number of input variables assigned to the receiver logic block approaches its maximum input width;
- and
- testing the cost function using a plurality of input variable assignments to determine an optimal input variable assignment.
A method for partitioning a plurality of logic functions amongst segments of a programmable logic device, wherein each segment comprises a plurality of logic blocks arranged from a first logic block to a last logic block, the plurality of logic blocks being configured to support a cascade chain extending from the first logic block to the last logic block for increasing a input width of cascaded product terms, and wherein each logic block has a maximum input width, the method comprising:
- identifying split functions within the logic functions whose input width exceeds the maximum input width for the logic blocks;
- providing a cost function that assigns a first cost to a number of outputs provided to each segment by the remaining segments and that assigns a second cost to the number of split functions within each segment;
- and
- testing the cost function with a plurality of partitions of the logic functions amongst the segments to identify an optimal partitioning.
A processor for configuring a programmable logic device to implement a desired logic function, wherein the programmable logic device includes a plurality of logic blocks, each logic block having a maximum input width, the processor comprising:
- a software fitting engine operable to identify functions within the desired logic functions whose input width exceeds the maximum input width such that the identified functions must be split between a feeder logic block and a receiver logic block within the programmable logic device, the software fitting engine being further operable to provide a cost function that assigns a first cost to a number of product terms cascaded from the feeder logic block to the receiver logic block and also assigns a second cost that increases as a number of input variables assigned to the receiver logic block approaches its maximum input width, the software fitting engine being operable to test the cost function using a plurality of input variable assignments to determine an optimal input variable assignment.
Dependencies are inferred from the claim text.