System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains

A system, used in a simulation of a design of a digital integrated circuit chip, to generate a number of global scan chains within said design of said chip, said system comprising:

• a design simulation tool;
• a set of initial chip design definition files organized as discrete blocks with each discrete block comprising sub-chains of flip-flops, wherein respective lengths of said sub-chains are generally similar within all of said discrete blocks, and wherein said set of initial chip design definition files is input into said simulation tool;
• and
• a set of modified chip design definition files generated by said simulation tool by processing said set of initial chip design definition files, and wherein said set of modified chip design definition files comprises said number of global scan chains funned by linking said sub-chains of flipflops within and across said discrete blocks.

A method for forming a plurality of substantially balanced global scan chains in a modular integrated circuit design, the method comprising:

• organizing the integrated circuit design into a plurality of discrete blocks, wherein each of the discrete blocks comprises a plurality of scan chain elements;
• generating one or more scan sub-chains in each of the discrete blocks, wherein each of the scan sub-chains comprises a plurality of the scan chain elements communicatively coupled, and wherein respective lengths of the scan sub-chains are generally similar within all of the discrete blocks;
• and
• generating the substantially balanced global scan chains, each of which comprises a plurality of the scan subchains serially and communicatively coupled, wherein at least one of the substantially balanced global scan chains comprises one of the scan sub-chains from a first of the discrete blocks serially and communicatively coupled to one of the scan sub-chains from a second of the discrete blocks.

A system for generating a plurality of global scan chains in an integrated circuit design, the system comprising:

• first computer memory comprising information of an integrated circuit design sub-divided into discrete blocks, each of the discrete blocks comprising one or more scan sub-chains, each scan sub-chain comprising a plurality of serially and communicatively coupled scan chain elements, wherein respective lengths of the scan sub-chains are generally similar within all of the discrete blocks;
• a processor communicatively coupled, to the first computer memory;
• second computer memory coupled to the processor comprising executable instructions that, when executed, cause the processor to generate an output signal comprising information of a plurality of substantially balanced global scan chains, each of the substantially balanced global scan chains comprising a plurality of the scan sub-chains serially and communicatively coupled, at least one of the substantially balanced global scan chains comprising one of the scan sub-chains from a first of the discrete blocks serially and communicatively coupled to one of the scan sub-chains from a second of the discrete blocks;
• and
• third computer memory coupled to the processor that receives the output signal comprising information of a plurality of substantially balanced global scan chains from the processor and stores the information of a plurality of substantially balanced global scan chains.