Method and apparatus for decomposing a region of an integrated circuit layout
AssigneeCadence Design Systems, Inc.
InventorsSteven Teig, Andrew Caldwell
Life of this patent
Estimating the term…
Abstract
Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit (“IC”) layout. The region contains several routable elements. Based on the routable elements, the method defines a plurality of nodes in the region. It then triangulates the region based on the nodes. The method then uses the triangles to define routes in the region.
Claims9
A method of decomposing a region of an integrated circuit (“IC”) layout, the region containing a plurality of routable elements, the method comprising:
- a) based on the routable elements, defining a plurality of nodes in the region, wherein defining the nodes comprises defining nodes at a boundary of the elements;
- b) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.
A method of decomposing a region of an integrated circuit(“IC”) layout, the region containing a plurality of routable elements and a set of obstacles, the method comprising:
- a) defining a plurality of nodes based on the obstacles, wherein defining the nodes comprises defining nodes at a boundary of the obstacles;
- b) based on the routable elements, defining a plurality of nodes in the region, wherein defining the nodes in the region comprises defining nodes at a boundary of the routable elements;
- c) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.
A computer readable medium that stores a computer program for decomposing a region of an integrated circuit (“IC”) layout, the region containing a plurality of routable elements, the computer program comprising instructions for:
- a) based on the routable elements, defining a plurality of nodes in the region, wherein the instructions for defining the nodes comprises instructions for defining nodes at a boundary of the routable elements;
- b) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.
A computer readable medium of that stores a computer program for decomposing a region of an integrated circuit (“IC”) layout, wherein the region contains a set of obstacles, the computer program comprising instructions for:
- a) defining a plurality of nodes based on the obstacles;
- wherein the instructions for defining the nodes comprises instructions for defining nodes at a boundary of the routable elements;
- b) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.
A method of decomposing a region of an integrated circuit (“IC”) layout, the region containing a plurality of obstacles, the method comprising:
- a) based on the obstacles, defining a plurality of nodes in the region;
- wherein defining the nodes comprises defining nodes at a boundary of the obstacles;
- b) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.
Dependencies are inferred from the claim text.