Method of optimizing signal lines within circuit, optimizing apparatus, recording medium having stored therein optimizing program, and method of designing circuit and recording medium having stored therein program for designing circuit

A recording medium having stored therein a program for forcing a computer to aid in designing a circuit having a clock signal supplying source and a plurality of flip-flop cells which are supplied with a dock signal from the clock signal supplying source, the program forcing the computer to carry out sequentially the following, comprising:

• synthesizing logic of circuit designing contents described in a register transfer level so as to create a first netlist which regulates a connection relationship between the flip-flop cells constituting a circuit to be designed;
• executing a floorplan by using the first netlist so as to create a clock tree of the circuit to be designed, and creating a second netlist containing one or more buffer cells for driving the flip-flop cells based on the clock tree;
• arranging a clock layout of the circuit to be designed based on floorplan information and the second netlist obtained by executing the floorplan so that the clock layout contains an initial placement of the buffer cells, the flip-flop cells, and clock signal lines connecting the one or more buffer cells and the flip-flop cell;
• and
• effecting an ordinary net wiring except for the clock signal lines after arranging the clock layout, wherein
• in the initial placement, the program causes the computer to adjust a number of buffer stages so that each of the circuit paths extending from the clock signal supplying source to the flip-flop cells consists of the same number of buffer stages so that signal delay times of clock signals supplied from the clock signal supplying source to each of the flip-flop cells are equal.

An apparatus for designing a circuit having a clock signal supplying source and a plurality of flip-flop cells which are supplied with a clock signal from the clock signal supplying source, comprising:

• means for synthesizing logic of circuit designing contents described in a register transfer level so as to create a first netlist which regulates a connection relationship between the flip-flop cells constituting a circuit to be designed;
• means for executing a floorplan by using the first netlist so as to create a clock tree of the circuit to be designed, and creating a second netlist containing one or more buffer cells for driving the flip-flop cells based on the clock tree;
• means for arranging a clock layout of the circuit to be designed based on floorplan information and the second netlist obtained by executing the floorplan so that the clock layout contains an initial placement of the buffer cells, the flip-flop cells, and clock signal lines connecting the one or more buffer cells and the flip-flop cells;
• and
• means for effecting an ordinary net wiring except for the clock signal lines after arranging the clock layout, wherein
• in the initial placement, a number of buffer stages are adjusted so that each of the circuit path extending from the clock signal supplying source to the flip-flop cells consists of the same number of buffer stages so that signal delay times of clock signals supplied from the clock signal supplying source to each of the flip-flop cells are equal.