System and method for executing image computation associated with a target circuit
AssigneeFujitsu Limited
InventorsJawahar Jain, Subramanian K. Iyer, Amit Narayan, Debashis Sahoo, Christian Stangier
Life of this patent
Estimating the term…
Loading patent…
AssigneeFujitsu Limited
InventorsJawahar Jain, Subramanian K. Iyer, Amit Narayan, Debashis Sahoo, Christian Stangier
Estimating the term…
A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more operations may be executed in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit. An image associated with the target circuit may be partitioned into a plurality of leaves that may each represent a subset of a final image to be generated by a partitioned ordered binary decision diagram (POBDD) data structure. An analysis may be computed of one or more of the leaves using a selected one or both of conjunction and quantification operations separately.
An apparatus for verifying a property associated with a target circuit, comprising:
A method for verifying a property associated with a target circuit, composing:
Software for verifying a property associated with a target circuit, the software being embodied in a computer readable medium and including computer code such that when executed:
A system for verifying a property associated with a target circuit, comprising:
Dependencies are inferred from the claim text.