Layout correction algorithms for removing stress and other physical effect induced process deviation

A method for creating a mask set from a physical layout for an integrated circuit (IC), the physical layout comprising a plurality of layout elements, the mask set to be used with a selected process, the method comprising:

• determining detailed characteristics for a physical effect of the selected process from a test chip;
• and
• applying a dimensional modification to at least one of the plurality of layout elements to compensate for the physical effect, based on the detailed characteristics
• wherein the step of applying the dimensional modification comprises adjusting the physical layout to generate a compensated physical layout.

A system for applying physical effect compensation to a physical layout for an IC, the system comprising:

• a detection module for identifying affected layout elements in the physical layout subject to a physical effect;
• and
• a compensation module for applying dimensional modifications to the affected layout elements to compensate for the physical effect
• wherein applying dimensional modifications to the affected layout elements comprises adjusting the physical layout to generate a compensated physical layout.