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US 7,032,149 B2Granted
Apparatus and method for adapting a level sensitive device to produce edge-triggered behavior
AssigneeIntel Corporation
InventorJohn C. Reynolds, Jr.
Life of this patent
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Abstract
A circuit for adapting a level sensitive memory device to exhibit edge-triggered behavior. The adapter circuit can be used with testing modules that expect edge-triggered behavior. The adapting circuit may include address decoding circuitry and output storage and delay circuitry.
Claims20
A device comprising:
- a first circuit to detect a self test mode;
- and
- a second circuit coupled to the first circuit to convert a level sensitive device output to an edge triggered output form.
An system comprising:
- a bus;
- a processor coupled to the bus;
- a input output controller coupled to the bus;
- a random access memory device coupled to the input output controller;
- a first circuit coupled to the random access memory device to select between a level sensitive output form and an edge triggered output form;
- and
- a second circuit coupled to the first circuit to covert a level sensitive output form to an edge triggered output form.
4 more elements
A method comprising:
- receiving a mode selection signal;
- converting a level sensitive device output to an edge triggered output format;
- and
- selecting one of a level sensitive output form and an edge triggered output form.
1 more element
A device comprising:
- a means for converting a level sensitive device output to an edge triggered output format;
- and
- a means for selecting one of a level sensitive output format and an edge triggered output format.
A machine-readable medium that provides instructions, which when executed by a machine cause the machine to perform operations comprising:
- receiving a mode selection signal;
- converting a level sensitive device output to an edge triggered output format;
- and
- selecting one of a level sensitive output form and an edge triggered output form.
1 more element
Dependencies are inferred from the claim text.