Boundary scan circuit
AssigneeOki Electric Industry Co., Ltd.
InventorHitoshi Tanaka
Life of this patent
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Abstract
An electronic device includes a first circuit, a second circuit, and a boundary scan circuit. The boundary scan circuit includes a boundary scan register having a first cell connected to an input node of the first circuit, and a second cell connected between an output node of the first circuit and an input node of the second circuit. The second cell has a latch flip-flop. The boundary scan circuit also includes an interface that enables and disables the latching operation of the latch flip-flop according to an input instruction code. While the latching operation is disabled, the output from the latch flip-flop to the second circuit remains unchanged. In this state, the boundary scan circuit can be used to test the first circuit without unintended effects on the second circuit.
Claims20
A boundary scan circuit integrated into a Joint Test Action Group (JTAG) device for testing a first circuit in the JTAG device, the first circuit having an input node and an output node, the JTAG device also including a second circuit having an input node coupled to the output node of the first circuit, the boundary scan circuit comprising:
- a boundary scan register having a first cell connected to the input node of the first circuit, and a second cell connected between the output node of the first circuit and the input node of the second circuit, the second cell having a latch flip-flop supplying latched data to the second circuit;
- and
- a Test Access Port (TAP) interface controlling the boundary scan register, the TAP interface enabling and disabling a latching operation by the latch flip-flop in the second cell according to an input instruction code.
A method of testing a first circuit in a JTAG device, the first circuit having an input node and an output node, the JTAG device also including a second circuit and a boundary scan register, the second circuit having an input node coupled to the output node of the first circuit, the boundary scan register having a first cell connected to the input node of the first circuit and a second cell connected between the output node of the first circuit and the input node of the second circuit, the second boundary scan cell having a latch flip-flop supplying latched data to the second circuit, the method comprising;
- setting control data in the latch flip-flop for output to the second circuit;
- disabling further latching operations by the latch flip-flop;
- supplying test input data to the first circuit through the first cell in the boundary scan register;
- obtaining test output data from the first input circuit through the second cell in the boundary scan register;
- and
- repeating the steps of supplying test input data and obtaining test output data, the latching operation by the latch flip-flop remaining disabled.
Dependencies are inferred from the claim text.