System for dynamic re-allocation of test pattern data for parallel and serial test data patterns

An automated test equipment (ATE) system comprising:

• a single memory for storing parallel and serial data vector sequences;
• a plurality of parallel in/parallel out shift registers, each having 2n outputs, coupled to said single memory;
• and,
• a plurality of pins, wherein each output of said parallel in/parallel out shift registers is coupled to a pin by a multiplexer and a register, and
• wherein every other output of each of said parallel in/parallel out shift registers is also coupled to n pins.

An automated test equipment (ATE) system comprising:

• a single memory for storing parallel and serial data vector sequences;
• a parallel in/parallel out shift register comprising 2n outputs, wherein n is an integer greater than 2, coupled to said single memory;
• and,
• 2n pins, wherein each of said 2n pins are coupled to n outputs of said parallel in/parallel out shift register by a circuit comprising a multiplexer having n inputs.

An automated testing equipment (ATE) system comprising:

• a signal memory for storing both serial vector data and parallel vector data for application to tester pins, said single memory comprising a plurality of data outputs which are divided into a plurality of segments;
• a serial shift register comprising parallel inputs and parallel outputs, said serial shift register coupled to a segment of said plurality of segments and wherein each cell of said serial shift register receives a respective data output of said single memory;
• and
• a plurality of pin circuits coupled to said serial shift register, wherein each pin circuit is coupled to a respective tester pin and, wherein further, said plurality of pin circuits allow each tester pin to receive serial vector data from two or more cells of said serial shift register during serial operation.

An automated testing equipment (ATE) system comprising:

• memory for storing serial vector data and parallel vector data for application to tester pins, said memory comprising a plurality of data outputs which are divided into a plurality of segments;
• a serial shift register comprising parallel inputs and parallel outputs, said serial shift register coupled to a segment of said plurality of segments and wherein each cell of said serial shift register receives a respective data output of said memory;
• and
• a plurality of pin circuits coupled to said serial shift register, wherein each pin circuit is coupled to a respective tester pin and, wherein further, said plurality of pin circuits allow each tester pin to receive serial vector data from every other cell of said serial shift register during serial operation.