Memory circuit having parity cell array

A memory circuit, having:

• a real cell array for storing data;
• a parity or error correction code (ECC) generating circuit for generating a parity bit or an ECC from data of said real cell array;
• a parity or ECC cell array for storing said parity bit or ECC;
• a data recovery section, which, in accordance with the parity bit or ECC read out from said parity or ECC cell array, recovers data read out from said real cell array;
• an output circuit, which outputs data from said real cell array via said data recovery section;
• and
• a test control circuit, which, at a test mode, prohibits the recovery of readout data by said data recovery section.

A memory circuit, having:

• a real cell array for storing data;
• a parity or error correction code (ECC) generating circuit for generating a parity bit or an ECC from data of said real cell array;
• a parity or ECC cell array for storing said parity bit or ECC;
• a data recovery section, which, in accordance with the parity bit or ECC read out from said parity or ECC cell array, recovers data read out from said real cell array;
• an output circuit, which outputs data from said real cell array;
• and
• a test control circuit, which, at a test mode, controls said output circuit so as to output data read out from said parity or ECC cell array.

A memory circuit, having:

• a real cell array for storing data;
• a parity or error correction code (ECC) generating circuit for generating a parity bit or an ECC from data of said real cell array;
• a parity or ECC cell array for storing said parity bit or ECC;
• a data recovery section, which, in accordance with the parity bit or ECC read out from said parity or ECC cell array, recovers data read out from said real cell array;
• an output circuit, which outputs data from said real cell array via said data recovery section;
• and
• a test control circuit, which, at a first test mode, prohibits the recovery of readout data in said data recovery section and, at a second test mode, controls said output circuit so as to output data read out from said parity or ECC cell array.

A memory circuit, having:

• a real cell array for storing data;
• a parity or error correction code (ECC) generating circuit for generating a parity bit or an ECC from data of said real cell array;
• a parity or ECC cell array for storing said parity bit or ECC;
• a data recovery section, which, in accordance with the parity bit or ECC read out from said parity or ECC cell array, recovers data read out from said real cell array;
• an output circuit, which outputs data from said real cell array;
• and
• a test control circuit, which, at a test mode, controls data read out from said parity or ECC cell array and data read out from said real cell array to be outputted separately.

A semiconductor memory, comprising:

• a plurality of real cell arrays, which have memory cells for storing each of the write data supplied via a plurality of data terminals;
• a parity generating circuit for generating parity data of said write data;
• a pattern generating circuit, which, at a test mode, generates a test pattern and outputs said generated test pattern to a transmission path for said write data;
• a first switch circuit, which selects said parity data at a normal operation mode and selects a portion of said write data at the test mode;
• a parity cell array, which has memory cells for storing said parity data or a portion of said write data selected by said first switch circuit;
• a data recovery circuit, which, at said normal operation mode, recovers said write data on the basis of real readout data read out from said real cell arrays and parity readout data read out from said parity cell array;
• and
• a test judgment circuit, which, at said test mode, receives real readout data read out from said real cell arrays and parity readout data read out from said parity cell array and judges a test result by comparing the real readout data and parity readout data with expected values.