Semiconductor device including test-facilitating circuit using built-in self test circuit
AssigneeRenesas Technology Corp.
InventorTetsushi Tanizaki
Life of this patent
Estimating the term…
Abstract
A test interface circuit, which has a simple pattern generator mounted on a semiconductor device having a mounted memory, consists of a command analysis section which analyses a command of three bits received from a tester, outputs an analysis result to a memory core and controls an operation of the memory core, and an address counter which counts addresses and outputs the addresses to the memory core in accordance with a counter control instruction of two bits received from the tester. It is, therefore, possible to make a circuit for testing the memory core small in scale and to decrease the number of pins for testing the memory core, so that it is possible to use an inexpensive tester and to reduce cost required to test the memory core.
Claims7
A semiconductor device, comprising:
- a memory core;
- and
- a first test circuit testing said memory core, wherein
- said first test circuit includes:
- a data generation circuit generating data written to said memory core;
- a data determination circuit determining the data read from said memory core;
- a command analysis section analyzing an externally applied command, outputting an analysis result to said memory core, and controlling an operation of said memory core;
- and
- an address counter counting addresses and outputting the addresses to said memory core in accordance with an externally applied counter control instruction.
A semiconductor device, comprising:
- a memory core;
- and
- a first test circuit testing said memory core, wherein
- said first test circuit includes:
- a data generation circuit generating data written to said memory core;
- a data determination circuit determining the data read from said memory core;
- a command analysis section analyzing an externally applied command, outputting an analysis result to said memory core, and controlling an operation of said memory core;
- an address counter counting addresses and outputting the addresses to said memory core in accordance with an externally applied counter control instruction;
- and
- a second test circuit generating a test pattern for a test performed to said memory core;
- wherein
- said first test circuit selectively executes a test of said memory core by said data generation circuit, said data determination circuit, said command analysis section and said address counter, and a test of said memory core by said second test circuit.
Dependencies are inferred from the claim text.