Bit error rate tester
AssigneeFinisar Corporation
InventorsFarhad Iryami, Paul Gentieu
Life of this patent
Estimating the term…
Abstract
The present invention is a bit error rate tester that may operate on network paths having devices that add or drop idles within a transmitted bit sequence. In particular, the bit sequence determines whether a received bit sequence is synchronized. If the received sequence is not synchronized or if a certain event/threshold is reached, then the bit error rate tester re-synchronizes the sequence prior to analysis. Also, the bit error rate detector is able to operate on high-speed networks and provide bit granularity measurements.
Claims39
An apparatus for measuring the bit error rate along a particular network path, the apparatus comprising:
- a first port that transmits a bit sequence onto a network at a rate above 3 Gigabits per second;
- a second port that receives the bit sequence from the network;
- a word aligner, coupled to receive the bit sequence from the second port, that ensures that the received bit sequence is synchronized;
- a start word detect module, coupled to receive the bit sequence from the word aligner, that identifies a start word in the received bit sequence;
- and
- a comparator, coupled to receive the bit sequence from the start word detect module, that calculates a bit error rate from the received bit sequence.
A method for detecting bit error rate within a network path, the method comprising the steps of:
- generating a bit sequence;
- transmitting the bit sequence onto a network at a rate higher than 3 Gigabits per second;
- receiving the bit sequence from the network;
- ensuring the received bit sequence is synchronized;
- identifying a start word within the received bit sequence;
- and
- comparing the received bit sequence to a regenerated bit sequence in order to identify errors in received bit sequence.
A system for measuring a bit error rate on a network path, the system comprising:
- a bit error rate tester, coupled to the network path, that transmits and receives a bit sequence at a rate above 3 Gigabits per second and used for testing the bit error rate on the network path;
- and
- at least one network device, coupled to the network path, that inserts idles within a data stream containing the bit sequence;
- wherein the bit sequence is an incremental bit sequence.
A bit error rate tester providing bit granularity measurements, the bit error rate tester comprising:
- a generator that produces a bit sequence;
- a bit sequence altering component, coupled to the generator, that alters the bit sequence prior to transmission onto a network path;
- a bit sequence regenerator, coupled to receive a copy of the altered bit sequence, that stores the altered bit sequence prior to transmission onto a network path;
- and
- a comparator, coupled to receive the bit sequence from the network path and a regenerated bit sequence from the bit sequence regenerator, that measures bit errors within the bit sequence received from the network path.
A method for measuring bit errors at bit granularity, the method comprising:
- generate a bit sequence;
- modifying the bit sequence in a bit error rate tester internal path;
- transmitting the modified bit sequence onto a network path;
- receiving the bit sequence from the network path;
- regenerating the modified bit sequence;
- and
- comparing the received bit sequence to the regenerated bit sequence.
Dependencies are inferred from the claim text.