Microprocessor design support for computer system and platform validation
AssigneeIntel Corporation
InventorsAyman G. Abdo, Cameron McNairy, Piyush Desai, Quinn W. Merrell
Life of this patent
Estimating the term…
Abstract
A validation FUB is a hardware system within the agent that can place a computer system in a stress condition. A validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions. The validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.
Claims27
A method of stress testing an integrated circuit, comprising:
- capturing a external bus transaction,
- if a request type of the transaction matches a triggering condition, generating a data request, and
- generating a harassing bus transaction based on the data request.
A stress testing method for a computer system, comprising:
- counting a number of external bus cycles that occur without onset of a new transaction on the external bus,
- determining if the number meets a threshold value,
- if so, generating a harassing transaction on the external bus.
An integrated circuit, comprising:
- a processor core, the processor core to operate in the domain of a first clock,
- a data request pipeline having an external bus interface that is in communication with an external bus, the external bus to operate in the domain of a second clock, where the second clock is different from the first clock, and
- a validation FUB having an input coupled to the external bus interface of the data request pipeline, the validation FUB to operate in the domain of the first clock, the validation FUB further comprising:
- a transaction latch coupled to the external bus interface, and
- a request library in communication with the transaction latch and having an output coupled to the data request pipeline, to store transaction request types according to an external bus protocol.
An integrated circuit, comprising:
- a processor core,
- a bus sequencing unit in communication with the processor core and an external bus, the bus sequencing unit comprising;
- an arbiter to receive a first data request,
- a cache memory to store data, and
- a transaction queue in communication with the arbiter and the cache memory to process the first data request, and
- a validation FUB in communication with the bus sequencing unit and the external bus, the validation FUB to receive the first data request from the arbiter to generate a second data request when the first data request matches a triggering condition.
An integrated circuit, comprising:
- a processor core,
- a bus sequencing unit in communication with the processor core and an external bus, the bus sequencing unit further comprising;
- an arbiter to receive a first data request,
- a cache memory to output a hit/miss signal in response to the first data request,
- a transaction queue in communication with the arbiter and the cache memory to process the first data request, and
- a validation FUB in communication with the bus sequencing unit and the external bus, the validation FUB to receive the hit/miss signal from the cache memory to generate a second data request when the hit/miss signal matches a triggering condition.
A diagnostic method for an integrated circuit, comprising:
- detecting an onset of a first transaction on an external bus,
- reading an address of the first transaction from the external bus, and
- in response to the detected transaction, issuing a read request in a second transaction on the external bus, the read request directed to the address read from said first transaction from the external bus.
A method of testing an integrated circuit, comprising:
- storing a request type in a register,
- observing a transaction on an external bus, and
- if the request type of the external bus transaction matches the request type stored in the register, generating a data request on the external bus.
A system comprising:
- a data bus;
- means for latching transaction data observed on the data bus, the transaction data to include a first data request to a first data address;
- means for determining whether a type of the first data request latched by said means for latching satisfies a trigger condition;
- means for forming a second data request based on the first data address if said means for determining determines that the trigger condition is satisfied;
- and
- means for posting the second data request to the data bus as a harassing transaction.
Dependencies are inferred from the claim text.