US 7,032,121 B2 · System for deriving desired output frequency by successively dividing clock signal frequency by ratios obtained by dividing clock signal frequency by common divisor and specific integer

Abstract

A signal is generated by providing a clock signal having a frequency (fosc). The clock frequency fosc is arithmetically divided by an output frequency (fo) associated with the signal to obtain a ratio R and a remainder given by x/y. The signal is derived from the clock signal by successively dividing the frequency (fosc) of the clock signal by one of R and R+1, such that a fraction of times that the frequency (fosc) of the clock signal is divided by R is given by 1-x/y and a fraction of times that the frequency (fosc) of the clock signal is divided by R+1 is given by x/y. In particular, the signal is derived by driving a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1-x/y and a fraction of times that the counter is driven to a count value of R+1 is given by x/y.

Claims12

Dependent claims

A method of generating a signal, comprising:

providing a clock signal having a frequency (fosc);
determining a common divisor between the clock frequency (fosc) and a reference frequency (fr), the signal having an output frequency (fo) given by k*fr where k is an integer;
dividing the clock frequency (fosc) by the common divisor to obtain a value N;
dividing the value N by the integer k to obtain a ratio R and a remainder given by r/k;
successively driving a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1−r/k and a fraction of times that the counter is driven to a count value of R+1 is given by r/k;
and
deriving the signal from an output of the counter.

4 more elements

A computer program product for generating a signal, comprising:

a computer readable storage medium having computer readable program code embodied therein, the computer readable program code comprising:
computer readable program code configured to provide a clock signal having a frequency (fosc);
computer readable program code configured to determine a common divisor between the clock frequency (fosc) and a reference frequency (fr), the signal having an output frequency (fo) given by k*fr where k is an integer;
computer readable program code configured to divide the clock frequency (fosc) by the common divisor to obtain a value N;
computer readable program code configured to divide the value N by the integer k to obtain a ratio R and a remainder given by r/k;
computer readable program code configured to successively drive a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1−r/k and a fraction of times that the counter is driven to a count value of R+1 is given by r/k;
and
computer readable program code configured to derive the signal from an output of the counter.

5 more elements

Dependencies are inferred from the claim text.

System for deriving desired output frequency by successively dividing clock signal frequency by ratios obtained by dividing clock signal frequency by common divisor and specific integer

Life of this patent

System for deriving desired output frequency by successively dividing clock signal frequency by ratios obtained by dividing clock signal frequency by common divisor and specific integer

Life of this patent

Abstract

Claims12