Method and apparatus for booting a microprocessor

A system for bootstrapping a plurality of slave processors from a plurality of volatile memory devices, comprising:

• a master processor with an associated flash device;
• a logic device for generating reset lines of the slave processors and deasserting the reset lines based on control signals from the master processor;
• the volatile memory devices storing boot code for the slave processors loaded from the flash device after the master processor has been bootstrapped;
• the slave processors each being connected to a separate volatile memory device, wherein when the reset lines of the slave processors are de-asserted, the slave processors bootstrap from the boot code stored in the volatile memory devices;
• wherein the master processor provides identity to each of the slave processors by posting information through the volatile memory devices.

A method for bootstrapping a second processor from either a flash device or a synchronous volatile memory device, comprising the steps of:

• bootstrapping a master processor;
• determining whether a flash bootstrap procedure or a volatile memory device bootstrap procedure has been selected for the second processor;
• setting a command register in a logic device to configure logic units for the selected bootstrap procedure;
• if the flash bootstrap procedure was selected:
• performing bootstrap procedure from the flash device associated with the second processor;
• if the volatile memory bootstrap procedure was selected:
• asserting reset lines of the second processor;
• loading boot code for the second processor from a flash device associated with the master processor into the volatile memory device;
• de-asserting the reset lines of the second processor;
• allowing a clock signal from the second processor to stabilize before providing the clock signal to the synchronous volatile memory device;
• and
• bootstrapping the second processor from the boot code stored in the volatile memory device.

A mechanism for bootstrapping a processor from a volatile memory device connected to the processor, comprising the steps of:

• means for asserting reset lines of the processor;
• means for loading boot code for the processor from a flash device into the volatile memory device;
• and
• means for de-asserting the reset lines of the processor,
• means for preventing the processor from reading a synchronous volatile memory device while a clock signal from the processor stabilizes after reset;
• wherein the processor performs the bootstrap procedure using the boot code stored in the volatile memory device while the processor provides the clock signal to the synchronous volatile memory device.

A computing system comprising:

• a nonvolatile memory device containing a master bootstrap process;
• a synchronous static random access memory containing a slave bootstrap process;
• a master processor in communication with the nonvolatile memory device, the master processor booting with the master bootstrap process, the master processor storing the slave bootstrap process on the synchronous static random access memory after the master processor has booted;
• a slave processor in communication with the synchronous static random access memory, the slave processor providing a clock signal to the synchronous static random access memory while booting with the slave bootstrap process stored on the synchronous static random access memory.

A computing system comprising:

• a nonvolatile memory device containing a master bootstrap process;
• a synchronous random access memory containing a slave bootstrap process;
• a master processor in communication with the nonvolatile memory device, the master processor booting with the master bootstrap process;
• a slave processor providing a clock signal to the synchronous random access memory;
• a data bus providing data communication between the synchronous random access memory and the slave processor;
• and
• a pulldown resister network on the data bus ensuring that the slave processor receives no-op instructions over the data bus during periods of clock instability.

A computing system comprising:

• a first volatile memory device containing a first identity;
• a second volatile memory device containing a second identity;
• a master processor in communication with the volatile memory devices, the master processor storing the first identity on the first volatile memory device, and the second identity on the second volatile memory device;
• a first slave processor in communication with the first volatile memory device, the first slave processor obtaining the first identity from the first volatile memory;
• and
• a second slave processor in communication with the second volatile memory device, the second slave processor obtaining the second identity from the second volatile memory.

A method for bootstrapping a processor from a synchronous memory device connected to the processor, comprising the steps of:

• loading the synchronous memory device with a boot code;
• resetting the processor after the boot code is loaded in the synchronous memory device;
• submitting no-op commands to the processor until the processor provides a reliable clock signal;
• supplying the reliable clock signal to the synchronous memory device;
• and
• loading the boot code from the synchronous memory device to the processor.

A computing system comprising:

• a nonvolatile memory device containing a slave bootstrap process;
• a synchronous volatile random access memory on which the slave bootstrap process is transferred after power up;
• a data bus;
• a master processor providing a control signal;
• a slave processor providing a memory control signal, receiving a reset control signal, and receiving data from the synchronous volatile random access memory over the data bus, the slave processor providing a clock signal to the synchronous volatile random access memory;
• a pulldown resistor network on the data bus ensuring that the slave processor receives no-op instructions over the data bus during periods of clock instability;
• and
• a programmable logic device acting in response to the control signal from the master processor and the memory control signal from the slave processor, the programmable logic device providing a reset control signal to the slave processor and a memory control signal to the synchronous volatile random access memory.