Configurable hardware register stack for CPU architectures
AssigneeLSI Logic Corporation
InventorPeter Korger
Life of this patent
Estimating the term…
Abstract
A circuit comprising a register stack and a control circuit. The register stack may be configured as (i) a plurality of segments addressable through a segment address signal and (ii) a plurality of registers within each of the plurality of segments. The plurality of registers are generally addressable through a register address signal. The control circuit may be configured to (i) store a plurality of register states, (ii) store a segment count signal, and (iii) present the segment address signal responsive to the plurality of register states, the segment count signal, and the register address signal.
Claims18
A circuit comprising:
- a register stack configured as (i) a plurality of segments addressable through a segment address signal and (ii) a plurality of registers within each of said plurality of segments, said plurality of registers being addressable through a register address signal;
- a control circuit connected to said register stack and configured to (i) store a plurality of register states, and (ii) store a segment count signal, wherein said control circuit comprises (A) a status circuit configured to present a gating signal responsive to both said register address signal and said register states and (B) a plurality of logic gates configured to present said segment address signal by logically ANDing said gating signal and said segment count signal;
- and
- a stack register connected to said control circuit and configured to present said register states to said control circuit, wherein each of said register states has one associated register of said registers.
A method of controlling a register stack comprising the steps of:
- (A) presenting a plurality of register states from a stack resister, wherein each of said register states has one associated register of a plurality of registers in said register stack;
- (B) storing said register states presented from said stack register;
- (C) storing a segment count;
- (D) presenting a gating signal responsive to both a register address and said register states;
- (E) logically ANDing said segment count with said gating signal to present a segment address;
- (F) addressing a plurality of segments within said register stack with said segment address;
- and
- (G) addressing said registers within one of said segments with said register address.
A circuit comprising:
- register stack means configured as (i) a plurality of segments addressable through a segment address and (ii) a plurality of registers within each of said plurality of segments, said plurality of registers being addressable through a register address;
- means for storing a plurality of register states;
- means for storing a segment count;
- means for presenting a gating signal responsive to both said resister address and said register states;
- means for presenting said segment address by logically ANDing said gating signal and said segment count;
- and
- means for presenting said register states to said means for storing said register states, wherein each of said register states has one associated register of said registers.
Dependencies are inferred from the claim text.