Method and apparatus for prioritized instruction issue queue in a processor
AssigneeInternational Business Machines Corporation
InventorsMichael Karl Gschwind, Valentina Salapura
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Abstract
An apparatus and method in a high performance processor for issuing instructions, comprising; a classification logic for sorting instructions in a number of priority categories, a plurality of instruction queues storing the instruction of differing priorities, and a issue logic selecting from which queue to dispatch instructions for execution. This apparatus and method can be implemented in both in-order, and out-of-order execution processor architectures. The invention also involves instruction cloning, and use of various predictive techniques.
Claims23
In a processor, an apparatus for issuing instructions, wherein said processor has a memory, a decoding unit, and an execution unit, said apparatus comprising:
- a classification logic adapted for prioritizing instructions in relation to one another and sorting said instructions in a number of priority categories, wherein said instructions come from said memory and are being decoded in said decoding unit prior of reaching said classification logic, and wherein said instructions sorted in said number of priority categories by said classification logic comprise cloned instructions;
- a plurality of instruction queues, wherein said queues contain said instructions in decoded form, wherein said plurality of said queues matches said number of said priority categories, and wherein each of said queues adapted to receive only one of said priority categories of said instructions from said classification logic, whereby said queues having same priority categories as said instructions, and wherein said cloned instructions and corresponding unmodified instructions from which said cloned instructions have been derived are found in different ones of said queues;
- and
- an issue logic to dispatch said instructions for execution in said execution unit of said processor, wherein said issue logic is operably coupled to said plurality of instruction queues and is selecting from which of said queues to dispatch said instructions for execution, wherein said issue logic has been designed to be cognizant of said priority categories of said queues.
In a processor, a method for issuing instructions, comprising the steps of:
- decoding instruction coming from a memory in a decoding unit and passing said instructions to a classification logic;
- prioritizing said instructions in relation to one another in said classification logic;
- sorting said instructions in a number of priority categories by said classification logic, wherein said instructions comprise cloned instructions;
- providing a plurality of instruction queues for containing said instructions in decoded form, wherein said plurality of said queues matching said number of said priority categories, and wherein each of said queues adapted to receive only one of said priority categories of said instructions from said classification logic, whereby said queues having same priority categories as said instructions, wherein said cloned instructions and corresponding unmodified instructions from which said cloned instructions have been derived are being sorted into different ones of said queues;
- and
- selecting from which of said queues to dispatch said instructions for execution in an execution unit of said processor by an issue logic, wherein said issue logic is operably coupled to said plurality of instruction queues and, wherein said issue logic has been designed to be cognizant of said priority categories of said queues.
Dependencies are inferred from the claim text.