Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache

A processor, comprising:

• a program counter;
• an instruction fetch unit coupled to said program counter, wherein said instruction fetch unit is configured to retrieve an address from said program counter, wherein said instruction fetch unit comprises:
• an instruction cache unit, wherein said instruction cache unit comprises an instruction cache and a prefetch buffer configured to store instructions;
• logic for performing a first hash on said address;
• logic for indexing in said instruction cache using said first hash on said address;
• logic for performing a second hash on said address;
• logic for indexing in said prefetch buffer using said second hash on said address;
• and
• logic for performing a third hash on said address;
• wherein said instruction cache unit further comprises:
• logic for comparing a value of said third hash on said address with a value stored in the indexed entry in an effective address array of said instruction cache;
• and
• logic for selecting instructions in said indexed entry of said prefetch buffer if said value stored in said indexed entry in said effective address array of said instruction cache does not match said value of said third hash on said address.

A method for selecting instructions in a prefetch buffer comprising the steps of:

• retrieving an address;
• performing a first hash on said address;
• indexing in an instruction cache using said first hash on said address;
• performing a second hash on said address;
• indexing in said prefetch buffer using said second hash on said address;
• performing a third hash on said address;
• comparing a value of said third hash on said address with a value stored in the indexed entry in an effective address array in a first way of said instruction cache;
• and
• selecting instructions in the indexed entry in said prefetch buffer if said value of said third hash on said address does not match said value stored in said indexed entry in said effective address array in said first way of said instruction cache.

A processor, comprising:

• a program counter;
• an instruction fetch unit coupled to said program counter, wherein said instruction fetch unit is configured to retrieve an address from said program counter, wherein said instruction fetch unit comprises:
• an instruction cache unit, wherein said instruction cache unit comprises an instruction cache and a prefetch buffer configured to store instructions;
• logic for performing a first hash on said address;
• logic for indexing in said instruction cache using said first hash on said address;
• logic for performing a second hash on said address;
• logic for indexing in said prefetch buffer using said second hash on said address;
• and
• logic for performing a third hash on said address;
• wherein said instruction cache unit further comprises:
• logic for comparing a value of said third hash on said address with a value stored in the indexed entry in an effective address array in a first way of said instruction cache;
• and
• logic for selecting instructions in the indexed entry in said prefetch buffer if said value of said third hash on said address does not match said value stored in said indexed entry in said effective address array in said first way of said instruction cache.