Memory controller for supporting a plurality of different memory accesse modes

A memory controller for supporting different memory modes, the memory controller comprising:

• a determining device for determining a memory mode, the determining device generating a memory selection signal;
• a memory writing device using the memory selection signal to provide a data selection signal, wherein the data selection signal is a first clock signal, the memory writing device further provides a data mask signal, wherein the data mask signal is chosen from a byte mask signal or a second clock signal, the memory writing device still further providing a memory data signal, wherein multiunit data are adapted to be carried therein, the memory data signal being controlled by the second clock signal or a third clock signal;
• and
• a memory reading device for receiving the data selection signal, the data mask signal, and a reference voltage, the memory reading device providing a differential signal and choosing the differential signal based upon the memory selection signal and delaying the differential signal for a predetermined time period for locking data on the memory data signal.

A data selection signal delay circuit adapted to be used in a memory controller for supporting different memory modes, the data selection signal delay circuit comprising:

• a first delay circuit for receiving a differential signal, and after delaying the differential signal for a first predetermined time period, the first delay circuit providing a first delay signal;
• a second delay circuit for receiving the differential signal, and after delaying the differential signal for a second predetermined time period, the second delay circuit providing a second delay signal;
• and
• a multiplexer for providing an output, wherein the output is based upon a selection between the first delay signal or the second delay signal and having the selection based upon information carried by a memory selection signal.

A controller coupled to a memory having a plurality of memory types, the controller being adapted to use at least one clock signal of a signal generator, the controller comprising:

• a determining device for determining a memory type, the determining device generating a memory type signal relating to the memory type;
• a writing device coupled to the determining device adapted to receive the memory type signal, the writing device processing received data according to the memory type signal and further providing a data mask signal chosen from a byte mask signal and a plurality of clock signals;
• and
• a reading device in information communication with the writing device and coupled to the determining device adapted to receive the memory type signal, the reading device being adapted to delay signals provided by the writing device passing therethrough for a predetermined time period and capture the same signals provided by the writing device thereafter, thereby different memory types are capable of being processed using a single controller.

A method for a memory controller adapted to control a plurality of memory types, comprising the steps of:

• determining a memory type;
• generating a memory type signal;
• providing a data mask signal chosen from a byte mask signal and a plurality of clock signals;
• receiving a memory data signal including the data mask signal;
• delay the memory data signal for a predetermined time period according to the memory type signal;
• and
• capturing the memory data.