Multiple cache coherency
AssigneeHewlett-Packard Development Company, L.P.
InventorsPaul L. Rogers, Robert F. Krick, Vipul Gandhi
Life of this patent
Estimating the term…
Abstract
A memory architecture with a multiple cache coherency includes at least one processor with a storage area in communication with a cache memory. A main bus transmits and receives data to and from the cache memory and the processor. A coherency control in communication with the cache memory and the processor is configured to determine an existence or location of data in the cache memory or the storage area in response to a data request from the main bus. The coherency control dispatches an existence or location result to the main bus.
Claims17
A memory architecture, comprising:
- at least one processor having a storage area;
- a cache memory in communication with the at least one processor to cache the at least one processor;
- a main bus in communication with the at least one processor and the cache memory to transmit and receive data to and from the cache memory and the at least one processor;
- a coherency control in communication with the cache and the at least one processor and configured to determine an existence or location of data in the cache or the storage area responsive to a data request from the main bus and dispatch a result indicating the existence or location of the data to the main bus,
- a return buffer buffering data transmission from the main bus to the cache and the at least one processor, wherein the coherency control is configured to communicate with the return buffer to determine the existence or location of the data in the return buffer;
- and
- a read queue configured to dispatch data from the cache, wherein the coherency control is in communication with the read queue to determine the existence or location of the data in the read queue;
- wherein the coherency control is configured to re-determine the existence or location of the data in the read queue, return buffer, storage area, and the cache if the coherency control determines that the data is in the return buffer or the read queue.
A method for conducting coherency control of a memory architecture, the method comprising the steps of:
- receiving a data request for data from a requesting entity along a main bus;
- querying a cache and a storage area of a processor to determine an existence or location of the data in the cache or the storage area, wherein the cache caches the processor;
- querying a return buffer that returns data to the cache and a read queue that dispatches data from the cache to the processor or the main bus;
- querying the return buffer, read queue, storage area, and the cache to determine the existence or location of the data if the data is determined to exist in the read queue or the return buffer;
- and
- dispatching a result to the requesting entity along the main bus.
A computer readable memory device comprising instructions for:
- reading a data request for data from a requesting entity along a main bus;
- querying a cache and a storage area of a processor to determine an existence or location of the data in the cache or the storage area, wherein the cache caches the processor;
- querying a return buffer that returns data to the cache and a read queue that dispatches data from the cache to the processor or the main bus;
- performing a query in the return buffer, read queue, storage area and the cache to determine the existence or location of the data if the data is determined to exist in the read queue or the return buffer;
- and
- dispatch a result to the requesting entity along the main bus.
Dependencies are inferred from the claim text.