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US 7,032,076 B2Granted
Prefetching data in a computer system
AssigneeIntel Corporation
InventorsEric A. Sprangle, Anwar Q. Rohillah
Life of this patent
Estimating the term…
Abstract
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.
Claims19
An apparatus comprising:
- a plurality of address buffers to receive and store a plurality of prefetch addresses;
- and
- a filter circuit coupled to the plurality of address buffers to compare the stored plurality of prefetch addresses with a received prefetch address, said filter circuit to discard the received prefetch address if the received prefetch address is equal to any one of the stored plurality of prefetch addresses;
- an input queue coupled to the filter circuit;
- an output queue;
- and
- a hardware prefetch engine coupled to the input queue and to the output queue.
4 more elements
A method comprising:
- receiving a first prefetch address;
- storing the first prefetch address;
- receiving a second prefetch address;
- comparing the received second prefetch address with the stored first prefetch address;
- discarding the received second prefetch address if the received second prefetch address is equal to the stored first prefetch address;
- and
- storing the received second prefetch address in an input queue if the received second prefetch address is not equal to the stored first prefetch address;
- wherein said input queue is coupled to a hardware prefetch unit, which is coupled to an output queue.
5 more elements
A computer system comprising:
- an external bus;
- an external memory coupled to the external bus;
- a processor core coupled to a cache memory and to the external memory;
- a plurality of address buffers to receive and store a plurality of prefetch addresses;
- and
- a filter circuit coupled to an input queue and to the plurality of address buffers to compare the stored plurality of prefetch addresses with a received prefetch address, said filter circuit to discard the received prefetch address if the received prefetch address matches any one of the stored plurality of prefetch addresses;
- a hardware prefetch engine coupled to the input queue and to an output queue.
4 more elements
Dependencies are inferred from the claim text.