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US 7,032,075 B2Granted
Instruction cache and microprocessor
AssigneeKabushiki Kaisha Toshiba
InventorIsao Katayama
Life of this patent
Estimating the term…
Abstract
In a central processing unit, caching is carried out for an instruction cache tag memory, so that, without making modifications to a conventional instruction cache controller, the number of times of access to the instruction cache tag memory, which consumes a large amount of electric power, is reduced, and low electric power consumption is attained.
Claims10
An instruction cache comprising:
- an instruction cache control circuit;
- an instruction cache tag memory;
- an instruction cache data memory;
- and
- an instruction cache tag access control circuit which is provided between the instruction cache control circuit and the instruction cache tag memory, the instruction cache tag access control circuit configured to monitor whether or not an instruction cache tag memory address in an access from the instruction cache control circuit to the instruction cache tag memory is the same as that in a previous access from the instruction cache control circuit to the instruction cache tag memory, without a non-jump instruction detecting signal being supplied from the instruction cache control circuit to the instruction cache tag access control circuit, to control whether or not access to the instruction cache tag memory is possible based on a status of equivalence of the instruction cache tag memory addresses determined by the monitoring.
2 more elements
A microprocessor in which an instruction cache is provided on the same semiconductor chip as a microprocessor circuit, in which the instruction cache comprises:
- an instruction cache control circuit;
- an instruction cache tag memory;
- an instruction cache data memory;
- and
- an instruction cache tag access control circuit which is provided between the instruction cache control circuit and the instruction cache tag memory, the instruction cache tag access control circuit configured to monitor whether or not an instruction cache tag memory address in an access from the instruction cache control circuit to the instruction cache tag memory is the same as that in a previous access from the instruction cache control circuit to the instruction cache tag memory, without a non-jump instruction detecting signal being supplied from the instruction cache control circuit to the instruction cache tag access control circuit, to control whether or not access to the instruction cache tag memory is possible based on a status of equivalence of the instruction cache tag memory addresses determined by the monitoring.
2 more elements
Dependencies are inferred from the claim text.