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US 7,032,038 B1Granted
Configurable peripheral devices
AssigneeXilinx, Inc.
InventorDavid B. Squires
Life of this patent
Estimating the term…
Abstract
A single integrated circuit can be designed to include a processor core and one or more configurable peripheral devices selectable by a user. Because the peripheral device is configurable, the user can select only the features he/she needs in the integrated circuit. As a result, the peripheral devices included in the integrated circuit do not have to be flexibly designed in the same manner as commercially available peripheral devices. Consequently, they are easy to use.
Claims18
An integrated circuit comprising:
- a processor core;
- a configurable peripheral device comprising a configurable logic block having circuitry capable of implementing a plurality of logic functions;
- a bus coupled between said processor core and said configurable peripheral device, said bus connecting said processor core and said configurable peripheral device without using a sub-processor;
- a programmable routing matrix coupled to said configurable logic block, said programmable routing matrix coupling signals to and from said configurable logic block;
- and
- an input/output block coupled to said programmable routing matrix, wherein said programmable routing matrix provides input/output routing for said configurable peripheral device by way of said input/output block without using a sub-processor;
- wherein said processor core, said configurable peripheral device and said bus are implemented on a field programmable gate array.
4 more elements
A system allowing a user to select peripheral devices in a programmable logic device, comprising:
- a menu system allowing said user to select one of a plurality of configurable peripheral devices;
- a processor core;
- a configurable peripheral device comprising a configurable logic block having circuitry capable of implementing a plurality of logic functions;
- a bus coupled between said processor core and said configurable peripheral device, said bus connecting said processor core and said configurable peripheral device without using a sub-processor;
- a programmable routing matrix coupled to said configurable logic block, said programmable routing matrix coupling signals to and from said configurable logic block;
- and
- an input/output block coupled to said programmable routing matrix, wherein said programmable routing matrix provides input/output routing for said configurable peripheral device by way of said input/output block without using a sub-processor;
- wherein said processor core, said configurable peripheral device and said bus are implemented on a field programmable gate array.
5 more elements
An integrated circuit comprising:
- a processor core;
- a universal asynchronous receiver transmitter circuit having a baud rate generator implemented in a configurable logic block having circuitry capable of implementing a plurality of logic functions;
- a bus coupled between said processor core and said universal asynchronous receiver transmitter circuit;
- a programmable routing matrix coupled to said configurable logic block, said programmable routing matrix coupling signals to and from said configurable logic block;
- and
- an input/output block coupled to said programmable routing matrix, wherein said programmable routine matrix provides input/output routing for said universal asynchronous receiver transmitter by way of said input/output block without using a sub-processor;
- wherein said processor core, said universal asynchronous receiver transmitter circuit and said bus are implemented on a field programmable gate array.
4 more elements
Dependencies are inferred from the claim text.