Hardware function generator support in a DSP

A control circuit for a pipelined Coordinate Rotation Digital Computer (CORDIC) comprising:

• a reset circuit adapted to reset at least a portion of the pipelined stages of the pipelined CORDIC;
• a first sequencing unit adapted to automatically enable clock pulses to the pipelined CORDIC such that a new calculation progress from a beginning of the pipelined CORDIC to an end of the pipelined CORDIC and to automatically disable the automatic application of clock pulses to the pipelined CORDIC when the computation is available at the end of the pipelined CORDIC;
• and a second sequencing unit adapted to provide a clock pulse to the pipelined CORDIC to advance a calculation from one stage to another where the second sequencing unit is configured to provide the clock pulse in response to an instruction to read an output of the pipelined CORDIC, wherein the first sequencing unit comprises a counter that is reset in response to a detection of a start instruction, where the first sequencing unit enables clock pulses when a count maintained by the counter is in a first range of counts, and where the first sequencing unit disables the automatic application of clock pulses when the count maintained by the counter is in a second range of count.