US 7,031,889 B1 · Method and apparatus for evaluating the design quality of network nodes

Abstract

A method and apparatus for evaluating the design quality of an integrated circuit design. The design to be evaluated comprises a plurality of static gates, such as, for example, NAND and NOR gates. The apparatus of the present invention comprises a computer configured to execute a rules checker program. The rules checker program analyzes each of the static gates to determine whether or not the gates meet acceptable noise immunity requirements. In order to perform this task, the rules checker program constructs models of each gate. The models emphasize or de-emphasize the strengths of certain FETs of the gate in response to noise on inputs to the gate for different logic states of the inputs. For each model, the rules checker program obtains a PFET-to-NFET width ratio. These ratios are utilized to obtain noise levels from a lookup table. Noise levels on the inputs to the gate are derived, either by calculation or simulation. These derived noise levels are then compared with the noise levels obtained from the lookup table to determine whether or not the gate being evaluated meets acceptable noise immunity requirements.

Claims20

Dependent claims

An apparatus for evaluating a gate to determine whether or not the gate has an acceptable immunity to noise, the apparatus comprising:

a computer configured to execute a rules checker program, the rules checker program receiving input relating to characteristics of a static gate contained in the integrated circuit, the gate comprising at least two field effect transistors, each field effect transistor having a width, the characteristics including the widths of the field effect transistors, the rules checker program analyzing the widths of the field effect transistors to determine whether or not the gate has an acceptable noise immunity.

A method for evaluating a gate to determine whether or not the gate has an acceptable immunity to noise, the method comprising the steps of:

receiving input in a computer relating to characteristics of a static gate contained in the integrated circuit, the gate comprising at least two field effect transistors, each field effect transistor having a width, the characteristics including the widths of the field effect transistors;
and
analyzing the widths of the field effect transistors in the computer to determine whether or not the gate has an acceptable noise immunity, wherein the computer executes a rules checker program which analyzes the widths to determine whether or not the gate has an acceptable noise immunity.

A computer-readable medium containing a rules checker computer program, the computer program evaluating a gate to determine whether or not the gate has an acceptable immunity to noise, the gate comprising at least two field effect transistors, each field effect transistor having a width, the characteristics including the widths of the field effect transistors, the program comprising:

code which analyzes the widths of the field effect transistors to determine whether or not the gate has an acceptable noise immunity.

Dependencies are inferred from the claim text.

Method and apparatus for evaluating the design quality of network nodes

Life of this patent

Method and apparatus for evaluating the design quality of network nodes

Life of this patent

Abstract

Claims20