Method and apparatus for performing testing of interconnections

A system configured to facilitate interconnect testing comprising:

• a first component comprising first core circuitry, first interface circuitry, a pattern buffer configured to store a pattern, and a first communication path coupling the first core circuitry to the first interface circuitry;
• a second component comprising second core circuitry, second interface circuitry, and a second communication path coupling the second core circuitry to the second interface circuitry, and interconnect circuitry coupling the first component to the second component, wherein a capture buffer is coupled to the first communication path for capturing the pattern transmitted by the first component via the interconnect circuitry as a captured pattern;
• and
• a link between the second component and the first component, where the link is distinct from the interconnect circuitry and is configured to transfer the captured pattern from the second component to the first component for comparison with the pattern.

A memory system configured to allow interconnect testing comprising:

• a memory controller comprising a controller pattern buffer configured to store a pattern;
• a memory device coupled to the memory controller, wherein the memory controller comprises core circuitry, interface circuitry, and a communication path coupling the core circuitry to the interface circuitry, wherein a capture buffer is coupled to the communication path for capturing the pattern transmitted by the memory controller as a captured pattern;
• interconnect circuitry between the memory device and the memory controller, where the interconnect circuitry is configured to transfer the pattern from the memory controller to the memory device;
• and
• a link between the memory device and the memory controller, where the link is distinct from the interconnect circuitry and is configured to transfer the captured pattern from the memory to the memory controller for comparison with the pattern.

A system configured to facilitate interconnect testing comprising:

• a first component comprising first core circuitry, first interface circuitry, a means for storing a test pattern, and a first communication means for coupling the first core circuitry to the first interface circuitry;
• a second component comprising second core circuitry, second interface circuitry, and a second communication means for coupling the core circuitry to the interface circuitry, and interconnection means for coupling the first component to the second component, wherein a means for capturing the test pattern received from the first component is coupled to the first communication means;
• and
• a link means between the second component and the first component, where the link means is distinct from the interconnection means and is configured to transfer the captured test pattern from the second component to the first component for comparison with the test pattern.

A method for performing testing of an interconnect between components of a system comprising the steps of:

• storing a first pattern in a controller;
• transmitting the first pattern from the controller to a component of the components over a first interconnect;
• receiving at the controller from the component, via a second interconnect distinct from the first interconnect, a captured first pattern corresponding to the first pattern;
• performing at the controller a first comparison to compare the captured first pattern to the first pattern;
• transmitting a second pattern from the controller to the component via the second interconnect;
• receiving at the controller from the component, via the first interconnect, a captured second pattern corresponding to the second pattern;
• performing at the controller a second comparison to compare the captured second pattern to the second pattern;
• identifying any interconnect faults of the first interconnect based on the first comparison and the second comparison.

A method for performing testing of an interconnect between components of a system comprising the steps of:

• storing a first pattern in a controller;
• transmitting the first pattern from the controller to a component of the components over a first interconnect;
• receiving at the controller from the component, via a second interconnect distinct from the first interconnect, a captured first pattern corresponding to the first pattern;
• performing at the controller a first comparison to compare the captured first pattern to the first pattern;
• receiving at the controller from the component, via the first interconnect, a captured second pattern corresponding to a second pattern stored in an embedded memory element of the component;
• performing at the controller a second comparison to compare the captured second pattern to a copy of the second pattern stored in an embedded memory element of the controller;
• identifying any interconnect faults of the first interconnect based on the first comparison and the second comparison.