System and method for testing a memory
AssigneeVirage Logic Corporation
InventorsNiranjan Behera, Bruce L. Prickett, Jr.
Life of this patent
Estimating the term…
Abstract
A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.
Claims23
A memory compiler implemented on a computer readable medium for compiling at least one self-Test and repair (STAR) memory instance, comprising:
- a code portion for generating a built-in self-test and repair (BISTR) processor associated with said at least one STAR memory instance;
- and
- a code portion for generating a test and repair wrapper operable to be integrated with said at least one STAR memory instance, wherein said test and repair wrapper functions, responsive to test information scanned in by said BISTR processor, to generate address, data and command signals for effectuating at least one test with respect to said STAR memory instance.
A method of testing a memory instance, comprising:
- scanning test information into a test and repair wrapper integrated with said memory instance, wherein said test and repair wrapper is generated by a memory compiler used for compiling said memory instance;
- providing a strobe control signal to said test and repair wrapper for signaling commencement of testing operations with respect to said memory instance;
- generating, by said test and repair wrapper, at least one of an address signal, a data signal and a command signal based on said scanned test information;
- and
- executing at least one test with respect to said memory instance responsive to said address, data and command signals generated in said test and repair wrapper.
A system for testing a memory instance, comprising:
- means for scanning test information into a test and repair wrapper integrated with said memory instance, wherein said test and repair wrapper is generated by a memory compiler used for compiling said memory instance;
- means for providing a strobe control signal to said test and repair wrapper for signaling commencement of testing operations with respect to said memory instance;
- and
- means associated with said test and repair wrapper for locally generating at least one of an address signal, a data signal and a command signal based on said scanned test information, wherein a test operation is executed with respect to said memory instance responsive to said locally generated address, data and command signals.
Dependencies are inferred from the claim text.