Method and circuit for DC measurement of phase uniformity of multi-phase clocks

A system for measuring phase uniformity of a multi-phase clock set, where the multi-phase clock set is a set of L clocks, each having frequency fdck and each having a different phase φm that satisfies φm+φoffset+2π(m/L)+Δφm index “m” is a non-negative integer in the range {0, . . . , L−1}, φoffset is a phase, and Δφm is an error term, said system including:

• DC phase difference signal generation circuitry, coupled and configured to generate at least one DC phase difference signal in response to a clock pair sequence, wherein the clock pair sequence is a sequence of pairs of the clocks of the multi-phase clock set, and the at least one DC phase difference signal is indicative of the phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence;
• and
• means for processing the at least one DC phase difference signal to generate an indication of the phase uniformity of the multi-phase clock set, wherein the DC phase difference signal generation circuitry includes:
• combinational logic configured to generate at least one binary signal in response to the clock pair sequence;
• and
• at least one low pass filter coupled to the combinational logic and configured to generate the at least one DC phase difference signal in response to the at least one binary signal.

A system for measuring phase uniformity of a multi-phase clock set, where the multi-phase clock set is a set of L clocks, each having frequency fdck and each having a different phase that satisfies φm=φofffset+2π(m/L)+Δφm, index “m” is a non-negative integer in the range {0, . . . , L−1}, φoffset is a phase, and Δφm is an error term, said system including:

• DC phase difference signal generation circuitry, coupled and configured to generate at least one DC phase difference signal in response to a clock pair sequence, wherein the clock pair sequence is a sequence of pairs of the clocks of the multi-phase clock set, and the at least one DC phase difference signal is indicative of the phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence;
• and
• means for processing the at least one DC phase difference signal to generate an indication of the phase uniformity of the multi-phase clock set,
• wherein the DC phase difference signal generation circuitry is configured to generate one said DC phase difference signal in response to the clock pair sequence, and the DC phase difference signal has a sequence of levels indicative of the phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence, and wherein the DC phase difference signal generation circuitry includes:
• combinational logic configured to generate a binary signal in response to the clock pair sequence;
• and
• a low pass filter coupled to receive the binary signal and configured to generate the DC phase difference signal in response to the binary signal.

A system for measuring phase uniformity of a multi-phase clock set, where the multi-phase clock set is a set of L clocks, each having frequency fdck and each having a different phase φm that satisfies φm=φoffset+2π(m/L)+Δφm, index “m” is a non-negative integer in the range {0, . . . , L−1}, offset is a phase, and Δφm, is an error term, said system including:

• DC phase difference signal generation circuitry, coupled and configured to generate at least one DC phase difference signal in response to a clock pair sequence, wherein the clock pair sequence is a sequence of pairs of the clocks of the multi-phase clock set, and the at least one DC phase difference signal is indicative of the phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence;
• and
• means for processing the at least one DC phase difference signal to generate an indication of the phase uniformity of the multi-phase clock set,
• wherein the DC phase difference signal generation circuitry is configured to generate one said DC phase difference signal in response to the clock pair sequence, and the DC phase difference signal has a sequence of levels indicative of the phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence, and wherein the means for processing is configured to generate a sequence of samples of the DC phase difference signal.

A system, comprising:

• a transmitter;
• a receiver;
• and
• a link coupled between the transmitter and the receiver, wherein the transmitter is configured to generate data using a multi-phase clock set, and to transmit the data and a reference clock over the link to the receiver, where the multi-phase clock set is a set of L clocks, each having frequency fdck and each having a different phase φm that satisfies φm=φoffset+2π(m/L)+Δφm, index “m” is a non-negative integer in the range {0, . . . , L−1}, φoffset is a phase, and Δφm is an error term,
• the receiver is configured to receive the data and the reference clock, and to generate a second multi-phase clock set in response to said reference clock, and
• the transmitter includes:
• a circuit for generating a DC phase difference signal for use in measuring phase uniformity of the multi-phase clock set, said circuit for generating the DC phase difference signal including:
• multiplexer circuitry having inputs coupled to receive at least some of the clocks of the multi-phase clock set and a pair of outputs, wherein the multiplexer circuitry is configured to assert a clock pair sequence to the outputs, the clock pair sequence is a sequence of pairs of the clocks of the multi-phase clock set, and each of said pairs of the clocks is a selected pair of the clocks received at the inputs;
• and
• DC phase difference signal generation circuitry, having inputs coupled to the outputs of the multiplexer circuitry, and configured to generate the DC phase difference signal in response to the clock pair sequence such that the DC phase difference signal is indicative of a phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence.

A system, comprising:

• a transmitter;
• a receiver;
• and
• a link coupled between the transmitter and the receiver, wherein the transmitter is configured to generate data using a multi-phase clock set, and to transmit the data and a reference clock over the link to the receiver,
• the receiver is configured to receive the data and the reference clock, and to generate a second multi-phase clock set in response to said reference clock, where the second multi-phase clock set is a set of L clocks, each having frequency fdck and each having a different phase φm that satisfies φb=φoffset+2π(m/L)+Δφm, index “m” is a non-negative integer in the range {0, . . . , L−1}, φoffset is a phase, and Δφm is an error term, and
• the receiver includes:
• a circuit for generating a DC phase difference signal for use in measuring phase uniformity of the second multi-phase clock set, said circuit for generating the DC phase difference signal including:
• multiplexer circuitry having inputs coupled to receive at least some of the clocks of the second multi-phase clock set and a pair of outputs, wherein the multiplexer circuitry is configured to assert a clock pair sequence to the outputs, the clock pair sequence is a sequence of pairs of the clocks of the second multi- phase clock set, and each of said pairs of the clocks is a selected pair of the clocks received at the inputs;
• and
• DC phase difference signal generation circuitry, having inputs coupled to the outputs of the multiplexer circuitry, and configured to generate the DC phase difference signal in response to the clock pair sequence such that the DC phase difference signal is indicative of a phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence.

A receiver configured to receive data and a reference clock, and to generate a multi-phase clock set in response to the reference clock, where the multi-phase clock set is a set of L clocks, each having frequency fdck and each having a different phase φm that satisfies φm=φoffset+2π(m/L)+Δφm, index “m” is a non-negative integer in the range {0, . . . , L−1}, φoffset is a phase, and Δφm is an error term, wherein the receiver includes:

• a circuit for generating a DC phase difference signal for use in measuring phase uniformity of the multi-phase clock set, said circuit for generating the DC phase difference signal including:
• multiplexer circuitry having inputs coupled to receive at least some of the clocks of the multi-phase clock set and a pair of outputs, wherein the multiplexer circuitry is configured to assert a clock pair sequence to the outputs, the clock pair sequence is a sequence of pairs of the clocks of the multi-phase clock set, and each of said pairs of the clocks is a selected pair of the clocks received at the inputs;
• and
• DC phase difference signal generation circuitry, having inputs coupled to the outputs of the multiplexer circuitry, and configured to generate the DC phase difference signal in response to the clock pair sequence such that the DC phase difference signal is indicative of a phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence.

A transmitter configured to generate data using a multi- phase clock set, where the multi-phase clock set is a set of L clocks, each having frequency fdck and each having a different phase φm that satisfies φm=φoffset+2π(m/L)+Δφm, index “m” is a non-negative integer in the range {0, . . . , L−1}, φoffset is a phase, and Δφm is an error term, wherein the transmitter is also configured to assert the data and a reference clock to a link, and wherein the transmitter includes:

• a circuit for generating a DC phase difference signal for use in measuring phase uniformity of the multi-phase clock set, said circuit for generating the DC phase difference signal including:
• multiplexer circuitry having inputs coupled to receive at least some of the clocks of the multi-phase clock set and a pair of outputs, wherein the multiplexer circuitry is configured to assert a clock pair sequence to the outputs, the clock pair sequence is a sequence of pairs of the clocks of the multi-phase clock set, and each of said pairs of the clocks is a selected pair of the clocks received at the inputs;
• and
• DC phase difference signal generation circuitry, having inputs coupled to the outputs of the multiplexer circuitry, and configured to generate the DC phase difference signal in response to the clock pair sequence such that the DC phase difference signal is indicative of a phase difference between the clocks of each of the pairs of the clocks in the clock pair sequence.

A method for measuring phase uniformity of a multi-phase clock set, where the multi-phase clock set is a set of L clocks, each having frequency fdck and each having a different phase that satisfies φm=φoffset+2π(m/L)+Δφm index “m” is a non-negative integer in the range {0, . . . L−1} φoffset is a phase, and φm is an error term, said method including the steps of:

• (a) generating at least one DC phase difference signal indicative of a phase difference between the clocks of each pair of clocks of a clock pair sequence, where the clock pair sequence is a sequence of pairs of clocks of the multi-phase clock set;
• and
• (b) processing the at least one DC phase difference signal to generate an indication of the phase uniformity of the multi-phase clock set,
• wherein step (a) includes the step of generating one said DC phase difference signal, and step (b) includes the steps of:
• processing said DC phase difference signal to generate the indication of the phase uniformity of the multi-phase clock set, and said DC phase difference signal has a sequence of levels, each of the levels being a DC voltage level indicative of the phase difference between the clocks of a different one of the clock pairs of the clock pair sequence, and
• generating a sequence of samples of the DC phase difference signal such that each of the samples is indicative of a phase difference between the clocks of one of the clock pairs of the clock pair sequence.