Balanced circuit arrangement and method for linearizing such an arrangement
AssigneeNokia Corporation
InventorsKalle Kivekäs, Aarno Pärssinen
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Abstract
The present invention relates to a balanced circuit arrangement and methods for linearizing and calibrating such a circuit arrangement wherein linearization is obtained by introducing a load imbalance between the output branches of the balanced circuit arrangement. Thus, a controllable extraneous imbalance is created between the output loads of the balanced circuit arrangement to thereby obtain a linearization by means of even-order non-linearity.
Claims19
A balanced circuit arrangement comprising:
- a) first transistor means coupled via first load means to a power source;
- b) second transistor means coupled via second load means to said power source;
- and
- c) linearity control means for linearizing said balanced circuit arrangement by adjusting said first and second load means into a load imbalance.
A method for linearizing a balanced circuit arrangement, comprising the steps of:
- a) providing a controllable load means in at least one output branch of said balanced circuit arrangement;
- and
- b) adjusting the load of said controllable load means to obtain a linearizing load imbalance in the output branches of said balanced circuit arrangement.
A method for calibrating a balanced circuit arrangement, comprising the steps of:
- a) measuring a DC output level or lowpass filtered level of said balanced circuit arrangement when no input signal is applied or when input signal changes have only a weak effect on the measured signal;
- b) supplying a test signal to the input of said balanced circuit arrangement and measuring the DC output level;
- c) determining a difference between said measured DC levels;
- and
- d) adjusting a load means in at least one output branch of said balanced circuit arrangement until said determined difference is minimized.
Dependencies are inferred from the claim text.