FM transmitter
AssigneeRenesas Technology Corp.
InventorMasaru Kokubo
Life of this patent
Estimating the term…
Abstract
An FM transmitter that can control start/idle of each of such devices as a buffer amplifier without using a sample-and-hold circuit for moving a PLL into open loop control, wherein a controller that controls a charging pump in the PLL to start/idle the FM modulation is controlled with use of a closed/open loop select signal of the PLL, a start/idle signal of the buffer amplifier, and a preamble detection signal. The power consumption of the FM transmission can be reduced, since both the buffer amplifier and the PLL in the FM transmitter can be started/idled together in a ganged manner.
Claims13
An FM transmitter, comprising:
- a phase lock loop including a charging pump,
- wherein said phase lock loop further includes a phase comparator, a loop filter, a voltage controlled oscillator, and a counter;
- an adder to add up a frequency shift to a signal of said phase lock loop, said frequency shift corresponding to a transmission signal;
- a controller to receive a signal regarding start and idle of said phase lock loop, and to output a control signal to control an output of said charging pump;
- and
- a buffer amplifier to input a signal from said phase loop look and to output a signal to an antenna,
- wherein said controller is coupled to further receive a start/idle signal of said buffer amplifier and to output a control signal to hold an output of said charging pump in a high resistance state, and
- wherein said phase lock loop is controlled so as to be held in closed loop control for a period from a start-up timing of said phase lock loop, and held in open loop control for other periods.
A transmitter to transmit a signal with FM modulation,
- wherein the transmitter receives a start/idle signal of a phase lock loop circuit and a start/idle signal of a buffer amplifier, and outputs a control signal to hold an output of a charging pump at a first level of resistance at which a bias current is substantially zero,
- wherein said phase lock loop circuit is moved into open loop control when the output of the charge pump is held at the first level of resistance, and
- wherein said signal to be transmitted has a preamble, and said phase lock loop circuit is controlled for the loop to be closed or opened based on said preamble.
A transmitter to transmit a signal with FM modulation,
- wherein the transmitter receives a start/idle signal of a phase lock loop circuit and a start/idle signal of a buffer amplifier, and outputs a control signal to hold an output of a charging pump at a first level of resistance at which a bias current is substantially zero,
- wherein said phase lock loop circuit is moved into open loop control when the output of the charge pump is held at the first level of resistance,
- wherein said transmitter includes a controller comprising:
- a delay circuit to delay a start/idle signal of said buffer amplifier;
- and
- a flip-flop circuit to receive an output of said delay circuit at one input terminal and a start/idle signal of said phase lock loop at the other input terminal, said flip-flop circuit being set by said start/idle signal of said phase lock loop and reset by said output of said delay circuit, and
- wherein said phase lock loop is controlled so as to be held in closed loop control between a start-up timing of said phase lock loop and a timing delayed by a certain time from said start-up of said buffer amplifier, and held in open loop control in other periods.
A transmitter to transmit a signal with FM modulation,
- wherein the transmitter receives a start/idle signal of a phase lock loop circuit and a start/idle signal of a buffer amplifier, and outputs a control signal to hold an output of a charging pump at a first level of resistance at which a bias current is substantially zero,
- wherein said phase lock loop circuit is moved into open loop control when the output of the charge pump is held at the first level of resistance,
- wherein said transmitter includes a controller comprising a preamble detector to detect a preamble signal included in said transmission signal and a flip-flop circuit to be set by said start/idle signal of said phase lock loop and reset by said output of said preamble detector, and
- wherein said phase lock loop is controlled so as to be held in closed loop control between a start-up timing of said phase lock loop and a transmission timing of said preamble signal, and held in open loop control in other periods.
Dependencies are inferred from the claim text.