Method, device and system for output impedance calibration that invariably maximizes hybrid performance
AssigneeKey Eye
InventorsKenneth C. Dyer, Hiroshi Takatori
Life of this patent
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AssigneeKey Eye
InventorsKenneth C. Dyer, Hiroshi Takatori
Estimating the term…
A hybrid system with adjustable on-chip components and a method calibrating the same invariably maximizes hybrid performance despite of on- and off-chip component mismatches and imperfections. The hybrid system has a main DAC, a replica DAC, and three or four resistors. Both DACs are directly connected to digital data. An adjustable resistor is connected to the main DAC and is calibrated such that output impedance is automatically adjusted to match an off-chip load impedance Z. A replica DAC current K is calibrated for optimum DC matching in presence of Z. An adjustable capacitor C2 is calibrated for slope-matching (bandwidth matching). If Z changes, the calibration procedure should be repeated for optimal performance. These three calibration mechanisms can be utilized individually or in combination. The present invention is compatible with both analog and digital echo-cancellers.
An output impedance calibration method for invariably maximizing hybrid performance, said method comprising one or more steps selected from the group consisting of:
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