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US 7,031,420 B1Granted
System and method for adaptively deskewing parallel data signals relative to a clock
AssigneeSilicon Graphics, Inc.
InventorsPhilip Nord Jenkins, Frank N. Cornett
Life of this patent
Estimating the term…
Abstract
A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. Each of the plurality of delayed signals is compared to a reference signal to detect changes in the skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in the detected skew.
Claims41
A method of reducing skew between a plurality of signals transmitted with a transmit clock, wherein the plurality of signals includes a first signal and a second signal, the method comprising:
- receiving the transmit clock and each of the plurality of signals;
- detecting skew between the received transmit clock and each of the received signals;
- adding delay to one or more of the plurality of received signals to compensate for the detected skew;
- phase comparing each of the plurality of delayed signals to a reference signal to detect changes in the detected skew, wherein phase comparing includes generating a clock early signal and a data early signal for each of the plurality of signals;
- and
- modifying the delay added to each of the plurality of delayed signals to adapt to changes in the detected skew;
- wherein adding delay includes:
- passing each of the plurality of received signals through a separate delay line;
- and
- setting delay as a function of the clock early and data early signals, wherein setting delay includes determining a minimum latency through the delay lines.
7 more elements
A method of reducing skew between a plurality of signals transmitted with a transmit clock, wherein the plurality of signals includes a first signal and a second signal, the method comprising:
- receiving the transmit clock and each of the plurality of signals;
- detecting skew between the received transmit clock and each of the received signals;
- adding delay to one or more of the plurality of received signals to compensate for the detected skew;
- phase comparing each of the plurality of delayed signals to a reference signal to detect changes in the detected skew;
- and
- modifying the delay added to each of the plurality of delayed signals to adapt to changes in the detected skew;
- wherein detecting skew includes:
- doubling the received transmit clock to form a doubled clock;
- and
- clocking a phase comparator circuit with the doubled clock.
7 more elements
A circuit for reducing skew between a plurality of signals transmitted with a channel clock, wherein the plurality of signals includes a first and a second signal, the circuit comprising:
- a first data capture circuit connected to the first signal, wherein the first data capture circuit includes a first delay line and a first skew detection circuit connected to the first delay line;
- a second data capture circuit connected to the second signal, wherein the second data capture circuit includes a second delay line and a second skew detection circuit connected to the second delay line;
- a delay line controller connected to the first and second delay lines and the first and second skew detection circuits, wherein the delay line controller receives skew indicator signals representing skew from each of said first and second skew detection circuits and controls delay added by said first and second delay lines;
- and
- a channel clock interface connected to the first and second skew detection circuits, wherein said channel clock interface frequency doubles the channel clock to form a doubled channel clock;
- wherein the first and second skew detection circuits detect skew as a function of the doubled channel clock.
3 more elements
A communication system, comprising:
- a transmitter, wherein the transmitter transmits a plurality of signals in parallel, wherein the plurality of signals includes a first and a second signal;
- and
- a receiver, wherein the receiver includes a deskewing circuit, wherein the deskewing circuit includes:
- a first data capture circuit connected to the first signal, wherein the first data capture circuit includes a first delay line and a first skew detection circuit connected to the first delay line;
- a second data capture circuit connected to the second signal, wherein the second data capture circuit includes a second delay line and a second skew detection circuit connected to the second delay line;
- a delay line controller connected to the first and second delay lines and the first and second skew detection circuits, wherein the delay line controller receives skew indicator signals representing skew from each of said first and second skew detection circuits and controls delay added by said first and second delay lines;
- and
- a channel clock interface connected to the first and second skew detection circuits, wherein said channel clock interface frequency doubles the channel clock to form a doubled channel clock;
- wherein the first and second skew detection circuits detect skew as a function of the doubled channel clock.
6 more elements
An integrated circuit, comprising:
- a transmitter, wherein the transmitter transmits a plurality of signals in parallel, wherein the plurality of signals includes a first and a second signal;
- and
- a receiver, wherein the receiver includes a deskewing circuit, wherein the deskewing circuit includes:
- a first data capture circuit connected to the first signal, wherein the first data capture circuit includes a first delay line and a first skew detection circuit connected to the first delay line;
- a second data capture circuit connected to the second signal, wherein the second data capture circuit includes a second delay line and a second skew detection circuit connected to the second delay line;
- a delay line controller connected to the first and second delay lines and the first and second skew detection circuits, wherein the delay line controller receives skew indicator signals representing skew from each of said first and second skew detection circuits and controls delay added by said first and second delay lines;
- and
- a channel clock interface connected to the first and second skew detection circuits, wherein said channel clock interface frequency doubles the channel clock to form a doubled channel clock;
- wherein the first and second skew detection circuits detect skew as a function of the doubled channel clock.
6 more elements
A method for establishing the phase relationship between a plurality of signals, including a first signal, wherein the plurality of signals are transmitted with a channel clock, the method comprising:
- initializing signal deskewing circuitry, wherein initializing includes driving the circuitry with a predefined sequence of data edges;
- providing a phase comparator;
- receiving the channel clock;
- frequency doubling the received channel clock to form a frequency doubled channel clock, wherein the frequency doubled channel clock has 2 edges per data bit and a 50% duty cycle;
- driving the phase comparator with the frequency doubled channel clock, wherein driving includes sensing the clock and determining an error signal indicating drift from the 50% duty cycle;
- determining a phase relationship between the first signal and the clock;
- setting delay for the first signal as a function of the phase relationship;
- and
- modifying the delay as a function of changes in the phase relationship.
6 more elements
In a system having a channel clock, a plurality of channel signals and delay lines for delaying the channel clock and the plurality of channel signals, a method of adaptively deskewing delays between the plurality of channel signals, comprising:
- determining phase relationships between the channel clock and the plurality of channel signals, wherein determining includes generating skew indicator signals for each of the plurality of signals;
- filtering each skew indicator signal to reduce jitter;
- initializing a data minus clock (DMC) value for each channel signal;
- increasing the value of the DMC value corresponding to a particular signal if that signal arrives early with respect to a reference signal;
- decreasing the value of the DMC value corresponding to a particular signal if that signal arrives late with respect to the reference signal;
- determining a minimum DMC value from the plurality of DMC values;
- if the minimum DMC value is greater than zero, setting delay of the clock delay line to a minimum;
- if the minimum DMC value is less than zero, setting delay of the clock delay line to the absolute value of the minimum DMC value;
- calculating a channel signal delay for each of the channel signals, wherein calculating a delay includes determining a difference between the minimum DMC value and the DMC value corresponding to each of the plurality of channel signals;
- and
- setting delay of each of the channel signal delay lines to the channel signal delay calculated for each of the channel signals.
8 more elements
Dependencies are inferred from the claim text.