Multiple user reconfigurable CDMA processor

A circuit, comprising:

• a multiple frequency generator serving as a source of N reference clock frequencies, where N is an integer greater than one;
• N frequency extender circuits receiving the N reference clock frequencies and generating N frequency extended output clock signals therefrom;
• a plurality of N seed slewers producing N seed update values;
• a plurality of N seed registers each one receiving one of the N seed update values and producing N seed masks therefrom;
• a plurality of N logic circuits each receiving one of the N seed masks and one of the N frequency extended output clock signals;
• each of the N logic circuits producing a pseudorandom sequence from the seed mask and the frequency extended output clock signal;
• and
• a plurality of N correlators, each said correlator receiving one of the N pseudorandom sequences and correlating the pseudorandom sequence with a CDMA pilot I channel signal to produce a plurality of N offsets.

A circuit, comprising:

• a multiple clock reference generator serving as a source of N reference clock frequencies, where N is an integer greater than one;
• N frequency extender circuits receiving the N reference clock frequencies and generating N frequency extended output clock signals therefrom;
• a plurality of N seed slewers producing N seed update values;
• a plurality of N seed registers each one receiving one of the N seed update values and producing N seed masks therefrom;
• a plurality of N logic circuits each receiving one of the N seed masks and one of the N frequency extended output clock signals;
• each of the N logic circuits producing a pseudorandom sequence from the seed mask and the frequency extended output clock signal;
• a plurality of N correlators, each said correlator receiving one of the N pseudorandom sequences and correlating the pseudorandom sequence with a CDMA pilot I channel signal to produce a plurality of N offsets;
• and
• a reconfigurable processor controlling the N frequencies produced by the multiple reference clock generator.

A circuit, comprising:

• means for generating N reference clock frequencies, where N is an integer greater than one;
• means for receiving the N reference clock frequencies and generating N frequency extended output clock signals therefrom;
• means for generating a plurality of N seed masks from a plurality of N seed update values;
• means for receiving the N seed masks and the N frequency extended output clock signals and producing a pseudorandom sequence from each of the N seed masks and frequency extended output clock signals;
• and
• a plurality of N correlators, each said correlator receiving one of the N pseudorandom sequences and correlating the pseudorandom sequence with a CDMA pilot I channel signal to produce a plurality of N offsets.