Multiplexer circuit and analogue-to-digital converter

A multiplexer circuit comprising at least two input channels and an output channel, each input channel comprising a first transmission gate which can be switched on by a select signal for connecting the input channel to the output channel, at least one of the input channels comprising a by-pass circuit for preventing a current flowing through the first transmission gate from reaching the other input channel, and a second transmission gate, said multiplexer circuit further comprising a control circuit for controlling said bypass circuit,

• wherein said control circuit comprises a sense circuit to control said bypass circuit by sensing a voltage in the input channel, and
• wherein said sense circuit is constructed and adapted to sense a voltage in the input channel at the input of said first transmission gate or between said first transmission gate and said second transmission gate, and
• wherein a pull-down bypass circuit is formed of a first NMOS transistor having a drain and a source, the drain of which is connected with an output of said first transmission gate and the source of which is connected with the ground level, and
• wherein said sense circuit is formed of a PMOS transistor and a second NMOS transistor in series, the second NMOS transistor having a source and a drain, the source of the second NMOS transistor being connected to ground level and the PMOS transistor having a source and a drain, the source being connected to an output of said first transmission gate, and
• wherein the drains of said PMOS transistor and said second NMOS transistor are connected to each other and to the gate of the first NMOS transistor in the bypass circuit.

A multiplexer circuit comprising at least two input channels and an output channel, each input channel comprising a first transmission gate which can be switched on by a select signal for connecting the input channel to the output channel, at least one of the input channels comprising a by-pass circuit for preventing a current flowing through the first transmission gate from reaching the other input channel, and a second transmission gate, said multiplexer circuit further comprising a control circuit for controlling said bypass circuit,

• wherein said control circuit comprises a sense circuit to control said bypass circuit by sensing a voltage in the input channel, and
• wherein said sense circuit is constructed and adapted to sense a voltage in the input channel at the input of said first transmission gate or between said first transmission gate and said second transmission gate, and
• wherein a pull-up bypass circuit is formed of a first PMOS transistor having a drain and a source, the drain of which is connected with an output of said first transmission gate and the source of which is connected with power supply voltage level, and
• wherein said sense circuit is formed of a second PMOS transistor and an NMOS transistor in series, the second PMOS transistor and the NMOS transistor each having a source and a drain, the source of the second PMOS transistor being connected to power supply voltage level and the source of the NMOS transistor being connected to an output of said first transmission gate, and
• wherein the drains of the second PMOS transistor and the NMOS transistor are connected to each other and to the gate of the first PMOS transistor in the bypass circuit.