Control cell management method of ATM switching system

A control cell management method of an Asynchronous Transfer Mode (ATM) switching system, comprising:

• determining a priority between transmission and reception of control cells by a processor when the control cells are transmitted and received using a shared data bus between the processor and ATM processing units;
• determining an arrival of new control cells in each of a plurality of control cell reception buffers, while transmitting output control cells using the shared data bus;
• storing an address of a pertinent control cell reception buffer buffering a first-arrived new control cell;
• receiving the first-arrived new control cell from the pertinent control cell reception buffer, wherein the receiving includes:
• transmitting the stored address of the pertinent control cell reception buffer to the processor after the transmission of the output control cells is complete,
• setting a physical layer address of the pertinent control cell reception buffer by the processor,
• obtaining the first-arrived new control cell from the pertinent control cell reception buffer using the set physical layer address, and
• transmitting the obtained first-arrived new control cell to the processor through the shared data bus;
• and
• determining the arrival of the new control cells in one of the plurality of control cell reception buffers.

A control cell processing method of a switching system, comprising:

• receiving a first-arrived control cell at a first buffer;
• receiving another control cell at a second buffer different than the first buffer;
• identifying the first buffer that receives the first-arrived control cell;
• and
• communicating the first-arrived control cell to a processor for processing, using a shared data bus, before processing a later-arrived control cell, the method additionally including:
• associating the processing of a control cell from each mth buffer of n buffers with a unique Smth state from a set of n states {S1, S2, S3, S4, . . . , Sn}, and
• transitioning from a current state of the n states to a next state of the n states when an ith buffer of the n buffers receives a subsequent control cell and the first-arrived control cell has been processed, wherein the next state is identified by the next higher priority state in the hierarchical sequence Si+1, Si+2, Si+3, . . . , Sn, S1, S2, S3, . . . , Si−1, where Si represents the current state, whose associated buffer contains the subsequent control cell.

A control cell switching apparatus, comprising:

• a processor that processes control cells communicated by the apparatus;
• a plurality of receive buffers that buffer the control cells communicated by an external device to the processor;
• a shared data bus between the processor and the receive buffers for communicating the control cells;
• and
• an input and output (I/O) controller that prioritizes the use of the shared data bus by the receive buffers, wherein
• the I/O controller identifies a first receive buffer of the receive buffers that receives a first-arriving control cell and communicates the first-arriving control cell to the processor using the shared data bus, before communicating a later-arriving control cell, wherein:
• the I/O controller associates the processing of a control cell from each mth buffer of n receive buffers with a unique Smth state from a set of n states {S1, S2, S3, S4, . . . , Sn},
• the I/O controller transitions from a current state of the n states to a next state of the n states when an ith buffer of the n receive buffers receives a subsequent control cell and the first-arriving control cell has been processed, and
• the next state is identified by the next higher priority state in the hierarchical sequence Si+1, Si+2, Si+3, . . . , Sn, S1, S2, S3, . . . , Si−1, where Si represents the current state, whose associated buffer contains the subsequent control cell.