Fixed phase clock and strobe signals in daisy chained chips
AssigneeIntel Corporation
InventorsStephen R. Mooney, Joseph T. Kennedy
Life of this patent
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Abstract
In some embodiments, a chip includes first and second ports to provide first and second received data signals and first and second received strobe signal, respectively. An internal clock signal has a fixed phase relationship to the first received strobe signal and the second received strobe signal has an arbitrary phase relationship with the internal clock signal. First and second write blocks latch the first and second received data signals synchronously with the first and second received strobe signals, respectively. Other embodiments are described and claimed.
Claims21
A chip comprising:
- a first port to provide a first received data signal and a first received strobe signal;
- a second port to provide a second received data signal and a second received strobe signal;
- circuitry to provide an internal clock signal with a fixed phase relationship to the first received strobe signal, wherein the second received strobe signal has an arbitrary phase relationship with the internal clock signal;
- and
- first and second write blocks to latch the first and second received data signals synchronously with the first and second received strobe signals, respectively.
A system comprising:
- a first chip and a second chip;
- and
- a third chip comprising:
- a first port coupled to first chip to provide a first received data signal and a first received strobe signal;
- a second port coupled to second chip to provide a second received data signal and a second received strobe signal;
- circuitry to provide an internal clock signal with a fixed phase relationship to the first received strobe signal, wherein the second received strobe signal has an arbitrary phase relationship with the internal clock signal;
- and
- first and second write blocks to latch the first and second received data signals synchronously with the first and second received strobe signals, respectively.
A chip comprising:
- a first port to provide a first received data signal and a first received strobe signal;
- a second port to provide a second received data signal and a second received strobe signal;
- circuitry to provide a phase adjusted internal clock signal with a fixed phase relationship to the first received strobe signal, wherein the second received strobe signal has an arbitrary phase relationship with the internal clock signal;
- and
- delay circuitry to delay the first received data strobe signal to latch the first data and to delay the second received data strobe signal to latch the second received data signal.
Dependencies are inferred from the claim text.