Internal power management scheme for a memory chip in deep power down mode

A deep power down circuit to save power in a low power memory chip, comprising:

• a) a plurality of pass gate circuits each coupled to outputs of charge pump circuits and voltage regulators internal to a low power memory chip;
• b) said pass gate circuits couple an external voltage of said low power memory chip to memory support circuits when the charge pumps, voltage regulators and voltage generators are turned off in a deep power down mode;
• and
• c) said charge pumps circuits and said voltage regulators are turned off at the beginning of a deep power down mode after a memory cell pre-charge is performed and pass gate circuits are turned on to provide power to said support circuits.

A deep power down circuit to save power in a low power memory chip, comprising:

• a) a plurality of pass gate circuits each coupled to outputs of charge pump circuits and voltage regulators internal to a low power memory chip;
• b) said pass gate circuits couple an external voltage of said low power memory chip to memory support circuits when the charge pumps, voltage regulators and voltage generators are turned off in a deep power down mode;
• and
• c) said pass gate circuits are replaced by grounding gates that are activated in said deep power down mode to ground the outputs of the charge pumps and voltage regulators internal to said low power memory chip.

A method for reducing memory chip power during a deep power down mode, comprising:

• a) preconditioning memory cells prior to applying a deep power down and
• b) entering said deep power down mode and reducing power of a memory chip, comprising:
• i) floating voltages used in preconditioning said memory cells;
• ii) replacing internal memory chip voltages not related to preconditioning said memory cells with voltages derived from an external voltage of said memory chip.

A system for conserving memory chip power during a deep power down mode, comprising:

• a) a means for turning off on-chip voltage regulators and charge pumps on a memory chip;
• b) a means for replacing output voltages of said voltage regulators and charge pumps during a deep power down mode;
• and
• c) the means for turning off on-chip regulators and charge pumps allows memory cell voltages to be floated.

A deep power down mode for low power memory chips, comprising:

• a) a low power memory chip;
• b) internal voltage circuits providing said memory chip with internal circuit power;
• c) a pass gate circuit connecting an externally derived voltage to said internal voltage circuits;
• d) a deep power down signal for controlling a reduced power of said memory chip;
• and
• e) said deep power down signal controlling said internal voltage circuits off and controlling pass gate circuits on during a deep power down mode to reduce power of said memory chip.