Refresh controller with low peak current
AssigneeHynix Semiconductor Inc.
InventorMin Young You
Life of this patent
Estimating the term…
Abstract
The disclosure relates to a memory such as a DRAM (dynamic random access memory), specifically to a refresh controller embedded in a memory. The refresh controller according to the present invention lowers the levels of peak currents by differentiating active times of a first bank enable signal and a second bank enable signal. The present invention has an advantage that there is no problem of substantially reducing a refresh prosecution time for a second portion because a delayed refresh enable signal is being disabled even while the second bank enable signal is being enabled.
Claims13
A refresh controller comprising a first element, a second element, and a third element, and outputting a first bank enable signal, a second bank enable signal, and a delayed refresh enable signal in response to a bank enable signal and a refresh enable signal, comprising:
- a first delay unit for outputting a second bank enable signal by delaying a first bank enable signal when a delayed refresh enable signal is active and outputting the bank enable signal as the second bank enable signal when the delayed refresh enable signal is inactive;
- a second delay unit for allowing a delayed bank enable signal to be in an enable state when the first bank enable signal or the second bank enable signal is active and allowing the delayed bank enable signal to be in a disable state when the first and second bank enable signals are inactive;
- and
- a latch for outputting the delayed refresh enable signal using a refresh enable signal when the delayed bank enable signal is inactive and maintaining a logical state of the delayed refresh enable signal outputted when the delayed bank enable signal is active.
A refresh controller, comprising:
- a first delay unit for outputting a second bank enable signal by delaying a bank enable signal inputted or outputting to first bank enable signal as the second bank enable signal as it is, in response to a delayed refresh enable signal;
- a second delay unit for outputting a delayed bank enable signal in response to a logical state of the first and second bank enable signals;
- and
- a latch for outputting the delayed refresh enable signal using a refresh enable signal or maintaining a logical state of the delayed refresh enable signal outputted regardless of the refresh enable signal, in response to the delayed bank enable signal.
Dependencies are inferred from the claim text.