Memory device and method having data path with multiple prefetch I/O configurations
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian Johnson, Troy A. Manning
Life of this patent
Estimating the term…
Abstract
A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
Claims5
A method of transferring data to a memory device in either a first operating mode or a second operating mode, the method comprising:
- in the first operating mode:
- transferring the data to each of N serial-to-parallel converters in the form of M bits of data applied in sequence to each of the N serial-to-parallel converters so that M sets of N-bit parallel data are applied to the N serial-to-parallel converters;
- transferring the data from each of the N serial-to-parallel converters to the memory device in the form of one set of M-bit parallel data so that N×M bits of parallel data are collectively transferred to the memory device from the N serial-to-parallel converters;
- and
- in the second operating mode:
- transferring the data to each of 2N serial-to-parallel converters in the form of M bits of data applied in sequence to each of the 2N serial-to-parallel converters so that M sets of 2N-bit parallel data are applied to the 2N serial-to-parallel converters;
- and
- transferring the data from each of the 2N serial-to-parallel converters to the memory device in the form of two sets of M/2-bit parallel data each so that a first set of N×M bits of parallel data are collectively transferred to the memory device from the 2N serial-to-parallel converters and a second set of N×M bits of parallel data are subsequently collectively transferred from the 2N serial-to-parallel converters.
Dependencies are inferred from the claim text.