Semiconductor memory device using VSS or VDD bit line precharge approach without reference cell

A semiconductor memory device comprising:

• a first memory cell;
• a second memory cell;
• a bit line connected to the first memory cell;
• a complementary bit line connected to the second memory cell;
• and
• a sense amplifier section, which senses and amplifies a voltage difference between the bit line and the complementary bit line,
• wherein the sense amplifier section comprises:
• two N-type sense amplifiers, each of which includes a pair of cross-coupled NMOS transistors, wherein the pair of NMOS transistors of each of the two N-type sense amplifiers have different current driving capabilities;
• and
• a P-type sense amplifier, which includes a pair of cross-coupled PMOS transistors,
• wherein the two N-type sense amplifiers are sequentially enabled at predetermined intervals.

A semiconductor memory device comprising:

• a first memory cell;
• a second memory cell;
• a bit line connected to the first memory cell;
• a complementary bit line connected to the second memory cell;
• and
• a sense amplifier section, which senses and amplifies a voltage difference between the bit line and the complementary bit line,
• wherein the sense amplifier section comprises:
• an N-type sense amplifier, which includes a pair of NMOS transistors having the same current driving capability;
• and
• two P-type sense amplifiers, each of which includes a pair of PMOS transistors having different current driving capabilities;
• wherein a sequence order in enabling the two P-type sense, amplifiers is determined depending on whether the first memory cell or the second memory cell is selected.

A semiconductor memory device comprising:

• a first memory cell;
• a second memory cell;
• a bit line connected to the first memory cell;
• a complementary bit line connected to the second memory cell;
• and
• a sense amplifier section, which senses and amplifies a voltage difference between the bit line and the complementary bit line,
• wherein the sense amplifier section comprises:
• two N-type sense amplifiers, each of which includes a pair of NMOS transistors having different current driving capabilities;
• and
• a P-type sense amplifier, which includes a pair of PMOS transistors having the same current driving capability,
• wherein a sequence order in enabling the two N-type sense amplifiers is determined depending on whether the first memory cell or the second memory cell is selected.

A semiconductor memory device comprising:

• a first memory cell;
• a second memory cell;
• a bit line connected to the first memory cell;
• a complementary bit line connected to the second memory cell;
• and
• a sense amplifier section, which senses and amplifies a voltage difference between the bit line and the complementary bit line,
• wherein the sense amplifier section comprises:
• an N-type sense amplifier, which includes a pair of cross-coupled NMOS transistors;
• and
• two P-type sense amplifiers, each of which includes a pair of cross-coupled PMOS transistors,
• wherein the two P-type sense amplifiers are sequentially enabled at predetermined intervals, and wherein a sequence order in which the two P-type sense amplifiers are enabled is determined depending on whether the first memory cell or the second memory cell is selected.